Intel® Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 12/13/2021
Public

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SYNCHRONIZATION_REGISTER_CHAIN_LENGTH

This setting specifies the maximum number of registers in a row to be considered as a synchronization chain. Synchronization chains are sequences of registers with the same clock, no fanout in between, such that the first register is fed by a pin, or by logic in another clock domain. These registers will be considered for metastability analysis (available for some families), and are also protected from optimizations such as retiming. When gate-level retiming is turned on, these registers will not be moved. The default length is device-specific.

Old Name

ADV_NETLIST_OPT_METASTABLE_REGS

Type

Integer

Device Support

  • Agilex
  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX
  • Intel® Stratix® 10

Notes

This assignment is included in the Analysis & Synthesis report.

This assignment supports synthesis wildcards.

Syntax


set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH <value>
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH -entity <entity name> <value>
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH -to <to> -entity <entity name> <value>