AN 447: Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems

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ID 683295
Date 3/28/2022
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Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems
Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems x
Receiver Level Requirements Guideline: Use Internal PCI Clamp Diode on the Pin Guideline: Use Series Termination Resistor Guideline: Select Appropriate Driver Interface Current between Supported Intel® Devices Document Revision History for AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems
Guideline: Use Internal PCI Clamp Diode on the Pin x
Measuring DC Current with PCI Clamp Diode
Guideline: Use Series Termination Resistor x
Selecting Appropriate Series Termination Resistor Value Example of Determining Series Termination Resistor Value
Guideline: Select Appropriate Driver x
Driver Selection Reference Current Limits Measurement Examples Evaluating Interface Using Driver Selection Method
Interfacing Intel® FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems

Driver Selection Reference

A driver can drive a receiver without termination even if it produces overshoot, undershoot, and ringing in the interface as long as it conforms to two key specifications of the receiver device.
  • Voltage threshold specifications—conformance ensures the correct logic-low and logic-high switching.
  • Maximum DC and AC input specifications—conformance ensures the reliability of the receiver device in the system over an extended period of time.

Use the current limits in the following table to measure if a driver meets the input specifications of the supported Intel® device for the target I/O standard without performing simulation.

Table 2.  Maximum Allowed Current Metrics Required to Drive Supported Intel® Devices without TerminationThis table lists the current limits that are the maximum allowable driver current values at the VOH levels of the respective I/O standards.
Driver Voltage Level I/O Standard VOH Level Receiver Bank VCCIO(V)1
2.5 ± 5% 3.0 ± 5% 3.3 ± 5%
2.5 V LVTTL 2.0 V No maximum limit No maximum limit 48 mA
3.0 V LVTTL 2.4 V 26 mA No maximum limit 26 mA
3.0 V LVCMOS VCCIO–0.2 V 8 mA No maximum limit 8 mA
3.3 V LVTTL 2.4 V 15 mA (30 mA) 2 No maximum limit 30 mA
3.3 V LVCMOS VCCIO–0.2 V 4 mA (8 mA)2 No maximum limit 12 mA

To determine if the driver meets the input specifications, perform the measurements on the driver pull-up I/V curve in the IBIS model of the device:

  • The pull-up I/V curve represents the current and voltage behavior of the driver when it is sourcing logic-high.
  • To account for the worst possible overshoot condition, take the measurement at the maximum allowable operating condition of the driver—at a low temperature and a high supply voltage.
  • The current limit does not represent the current strength of a driver associated with a particular I/O standard. You must perform the measurement on the I/V curve at the maximum condition.
A driver can drive to a supported Intel® device without requiring termination, for the desired interface setup, if the measured current of the driver is less than the current limit in the preceding table. If the driver current value is within the limits, the input signal to the receiver conforms to the following specifications:
  • The DC and AC maximum input voltage specifications of the receiver
  • The maximum DC current specifications of the PCI clamp diode
1 The Intel® Quartus® Prime software enables the PCI clamp diode for pins assigned as 3.3 V, 3.0 V, or 2.5 V LVTTL or LVCMOS I/O standards by default.
2 The value in brackets is the current limit for the driver if you disable the PCI clamp diode. For this combination, disabling the diode offers the driver slightly more margin. For other combinations, enabling the diode offers the driver better margin.
Level Two Title