1.5. JESD204B IP Core and AD9625 Configurations
The JESD204B IP core parameters (L, M and F) in this hardware checkout are natively supported by the AD9625 device. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9625 operating conditions.
The hardware checkout test implements the JESD204B IP core with the following parameter configuration.
Stratix V FPGA
| Configuration |
Setting |
||||
|---|---|---|---|---|---|
| LMF |
118 |
214 |
412 |
611 |
811 |
| HD |
0 |
0 |
0 |
1 |
1 |
| S |
4 |
4 |
4 |
4 |
4 |
| N |
16 3 |
12 |
12 |
12 |
12 |
| N’ |
16 |
16 |
16 |
12 |
16 |
| CS |
0 |
0 |
0 |
0 |
0 |
| CF |
0 |
0 |
0 |
0 |
0 |
| ADC Device Clock (MHz) |
2500 |
625 |
1250 |
2500 |
2500 |
| ADC Sampling Clock (MHz) |
156.25 |
625 |
1250 |
2500 |
2500 |
| FPGA Device Clock (MHz) 4 |
625 |
156.25 |
312.5 |
625 |
625 |
| FPGA Management Clock (MHz) |
100 |
100 |
100 |
100 |
100 |
| FPGA Frame Clock (MHz) 5 |
78.125 |
156.25 |
312.5 |
156.25 |
156.25 |
| FPGA Link Clock (MHz) 5 |
156.25 |
156.25 |
156.25 |
156.25 |
156.25 |
| Character Replacement |
Enabled |
Enabled |
Enabled |
Enabled |
Enabled |
| Data Pattern |
Ramp |
Ramp |
Ramp |
Ramp |
Ramp |
Arria 10 GX FPGA
| Configuration |
Setting |
||||
|---|---|---|---|---|---|
| LMF |
118 |
214 |
412 |
611 |
811 |
| HD |
0 |
0 |
0 |
1 |
1 |
| S |
4 |
4 |
4 |
4 |
4 |
| N |
16 6 |
16 6 |
16 6 |
12 |
12 |
| N’ |
16 |
16 |
16 |
12 |
16 |
| CS |
0 |
0 |
0 |
0 |
0 |
| CF |
0 |
0 |
0 |
0 |
0 |
| ADC Sampling Clock (MHz) |
2500 |
2500 |
2500 |
2500 |
2500 |
| FPGA Device Clock (MHz) 7 |
625 |
625 |
625 |
625 |
625 |
| FPGA Management Clock (MHz) |
100 |
100 |
100 |
100 |
100 |
| FPGA Frame Clock (MHz) 5 |
78.125 |
156.25 |
312.5 |
156.25 |
156.25 |
| FPGA Link Clock (MHz) 5 |
156.25 |
156.25 |
156.25 |
156.25 |
156.25 |
| Lane Rate (Gbps) | 6.25 | 6.25 | 6.25 | 6.25 | 6.25 |
| Character Replacement |
Enabled |
Enabled |
Enabled |
Enabled |
Enabled |
| Data Pattern 8 |
PRBS-23 Ramp |
PRBS-23 Ramp |
PRBS-23 Ramp |
PRBS-23 Ramp |
PRBS-23 Ramp |
3 This 16-bit test pattern is an output from the JESD204X test pattern block in the AD9625 device.
4 The device clock is used to clock the transceiver.
5 The frame clock and link clock is derived from the device clock using an internal PLL.
6 This 16-bit test pattern is an output from the JESD204X test pattern block in the AD9625 device.
7 The device clock is used to clock the transceiver.
8 The ramp pattern is for deterministic latency measurement test cases DL.1, DL.2, DL.3 only.