AN 712: Altera JESD204B MegaCore Function and ADI AD9625 Hardware Checkout Report

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ID 683294
Date 6/13/2016
Public
Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup for Stratix V Advanced Systems Development Kit 1.3. Hardware Setup for Arria 10 GX FPGA Development Kit 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and AD9625 Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. AN 712 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Descrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report

1.3. Hardware Setup for Arria 10 GX FPGA Development Kit

Figure 3. Hardware Setup

An Arria 10 FPGA Development Kit is used with the ADI AD9625 daughter card module attached to the FMC connector on the development board.

  • The AD9625 EVM derives power from the Arria 10 FMC connector.
  • Both the FPGA and ADC device clock must be sourced from the same clock source card with two different frequencies, one for the FPGA and one for ADC.
  • An internal on-board oscillator present on the AD9625 EVM provides 2.5 GHz device clock to the ADC.
  • The AD9625 divides the sampling clock by four (625 MHz) and supplies this divided clock through its DIVCLK pins to the FPGA.
  • For subclass 1, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9625 device.
Figure 4. System Diagram

The system-level diagram shows how the different modules connect in this design.

In this setup, where LMF=811, the data rate of the transceiver lanes is 6.25 Gbps. An on-board internal clock oscillator on the EVM board provides 2.5 GHz sampling clock to the ADC and divides the 2.5 GHz device clock by four to provide the clock (625 MHz) to the FPGA.

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