Mailbox Client Intel® FPGA IP User Guide

ID 683290
Date 12/04/2023
Public

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Document Table of Contents

1.3.1. Clock and Reset Interfaces

Table 2.  Clock and Reset Interfaces
Signal Role Width Direction Description
clk 1 Input Input clock to clock the IP. The maximum frequency is 250 MHz.
reset 1 Input Reset that resets the IP.

To reset the IP, assert the reset signal high for at least 2 clk cycles.

To ensure the Mailbox Client Intel® FPGA IP functions correctly when the device enters user mode, your design must include the Reset Release Intel® FPGA IP to hold the reset until the FPGA fabric entered user mode. Intel recommends using a reset synchronizer when connecting the user reset or output of the Reset Release IP to the reset port of the Mailbox Client IP. To implement the reset synchronizer, use the Reset Bridge Intel® FPGA IP available in the Platform Designer.
Note: For IP instantiation and connection guidelines in the Platform Designer, refer to the Required Communication and Host Components for the Remote System Update Design Example figure in the Intel® Stratix® 10 Configuration User Guide.
Note: For IP instantiation guidelines, refer to the Configuration User Guide.
irq 1 Output Interrupt signal. Drives the value of the AND of the interrupt status and interrupt enable registers.