1.3.3. AXI Manager Interface
The AXI manager interface is a standard advanced extensible interface (AXI). This interface is accessible when you enabled the crypto services features. The crypto services features are available for the Intel Agilex® 7 devices.
| Signal Role | Width | Direction | Description |
|---|---|---|---|
| AXI Manager Clock and Reset Signals | |||
| axi_in_clk | 1 | Input | AXI* interface clock. |
| axi_in_reset | 1 | Input | AXI* interface reset. |
| AXI Manager Write Address Channel Signals | |||
| axi_target_awid | 4 | Output | AXI* identification tag for write transaction. |
| axi_target_awaddr | 32 | Output | AXI* address of the first transfer in a write transaction. |
| axi_target_awlen | 8 | Output | AXI* length. Identifies the exact number of data transfers in a write transaction. |
| axi_target_awsize | 3 | Output | AXI* size. Identifies the number of bytes in each data transfer in a write transaction. |
| axi_target_awburst | 2 | Output | AXI* burst type. Indicates how address changes between each transfer in a write transaction. |
| axi_target_awlock | 1 | Output | Provides information about the atomic characteristics of a AXI* write transaction. |
| axi_target_awcache | 4 | Output | Indicates how a write transaction is required to progress through a system. |
| axi_target_awprot | 3 | Output | Protection attributes of a write transaction: privilege, security level, and access type. |
| axi_target_awqos | 4 | Output | Quality of Service identifier for a write transaction |
| axi_target_awvalid | 1 | Output | AXI* valid signal for a write transaction. Indicates that the write address channel signals are valid. |
| axi_target_awuser | 5 | Output | User-defined extension for the write address channel. |
| axi_target_awready | 1 | Input | AXI* ready signal for write address. Indicates that a transfer on the write address channel can be accepted. |
| AXI Manager Write Data Channel Signals | |||
| axi_target_wdata | 64 | Output | AXI* write data. |
| axi_target_wlast | 1 | Output | AXI* write transaction last data transfer. Indicates whether the current transfer is the last data transfer in a write transaction. |
| axi_target_wready | 1 | Input | AXI* ready signal for write data. Indicates that a write data channel transfer can be accepted. |
| axi_target_wvalid | 1 | Output | AXI* valid signal for write data. Indicates that a write data channel signals are valid. |
| axi_target_wstrb | 8 | Output | AXI* write strobes. Indicates the byte lane holding valid data. |
| AXI Manager Write Response Channel Signals | |||
| axi_target_bid | 4 | Input | AXI* identification tag for write response. |
| axi_target_bresp | 2 | Input | AXI* write response. Indicates write response status. |
| axi_target_bvalid | 1 | Input | AXI* valid signal for write response. Indicates that the write response channel signals are valid. |
| axi_target_bready | 1 | Output | AXI* ready signal for write response. Indicates that the write response channel transfer can be accepted. |
| AXI Manager Read Data Channel Signals | |||
| axi_target_rdata | 64 | Input | AXI* read data. |
| axi_target_rresp | 2 | Input | AXI* read response. Indicates read transfer status. |
| axi_target_rlast | 1 | Input | AXI* read transaction last data transfer. Indicates whether the current transfer is the last data transfer in a read transaction. |
| axi_target_rready | 1 | Output | AXI* read data channel ready signal. Indicates that a transfer on the read data channel can be accepted. |
| axi_target_rvalid | 1 | Input | AXI* valid signal for read data channel. Indicates that the read data channel signals are valid. |
| axi_target_rid | 4 | Input | AXI* identification tag for read data and response. |
| AXI Manager Read Response Channel Signals | |||
| axi_target_arid | 4 | Output | AXI* identification tag for read address transaction. |
| axi_target_araddr | 32 | Output | AXI* address of the first transfer in a read transaction. |
| axi_target_arlen | 8 | Output | AXI* length. Identifies the number of data transfers during the read transaction. |
| axi_target_arsize | 3 | Output | AXI* size. Identifies the number of bytes in each data transfer in a read transaction. |
| axi_target_arburst | 2 | Output | AXI* burst type. Indicates how address changes between each transfer in a read transaction. |
| axi_target_arlock | 1 | Output | Provides information about the atomic characteristics of a AXI* read transaction. |
| axi_target_arcache | 4 | Output | Indicates how a read transaction is required to progress through a system. |
| axi_target_arprot | 3 | Output | Protection attributes of a read transaction: privilege, security level, and access type. |
| axi_target_arqos | 4 | Output | Quality of Service identifier for a read transaction. |
| axi_target_arvalid | 1 | Output | AXI* valid signal for read transaction. Indicates that the read address channel signals are valid. |
| axi_target_aruser | 5 | Output | AXI* user-defined extension for the read address channel. |
| axi_target_arready | 1 | Input | AXI* read address channel ready signal. Indicates that a transfer on the read address channel can be accepted. |