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Ixiasoft
1.2. Block Diagram
The F-Tile CPRI PHY Intel® FPGA IP block diagram shows the main blocks, and internal and external connections for each variant.
Figure 1. IP Block Diagram
- The RS-FEC block is optional for the IP core variations that target 10.1376, 12.1651, and 24.33024 Gbps CPRI line rate.
- The soft reset controller implements the reset sequence of the IP core.
- The IP variation with 1.2288, 2.4576, 3.072, 4.9152, 6.144, and 9.8304 Gbps CPRI line rate include 8b/10b soft PCS.
- The IP variations that target CPRI line rates of 10.1376, 12.1651, and 24.33024 Gbps use 64b/66b hard PCS within the F-tile.
- It supports latency measurement for delay calculation between the FPGA pins to the core.