F-Tile CPRI PHY Intel® FPGA IP User Guide

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ID 683284
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile CPRI PHY Intel® FPGA IP 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. IP Registers 6. F-Tile CPRI PHY Intel FPGA IP User Guide Archives 7. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide
1. About the F-Tile CPRI PHY Intel® FPGA IP x
1.1. Supported Features 1.2. Block Diagram 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. F-Tile CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
3. IP Parameter Settings x
3.1. Design Example Parameters 3.2. Analog Parameters for F-Tile IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency 4.2.2. Calculation for 64b/66b Datapath
1. About the F-Tile CPRI PHY Intel® FPGA IP
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. IP Registers
6. F-Tile CPRI PHY Intel FPGA IP User Guide Archives
7. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

3.1. Design Example Parameters

Describes the F-Tile CPRI PHY IP Design Example Example Design and Analog Parameters tabs

Example Design Tab

If you select Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit for Target Development Kit, it only supports OSC_CLK_1_125MHZ for Device initialization clock. If you configure analog parameters other than the default and recommended values (Table 9), you see warnings to recommend you set to the default values.

Figure 6. Target Development Kit in the Example Design Tab
Figure 7. Warnings

Analog Parameters Tab

For all parameters in the Analog Parameters tab, refer to the Analog Parameters for F-Tile IPs.

When the CPRI rate is 6.1440G and below, the GUI has three extra analog parameters to configure:
  • RXEQ VGA Gain
  • RXEQ High Frequency Boost
  • RXEQ DFE Data Tap1
Figure 8. For CPRI Rates 9.8304G and Above
Figure 9. For CPRI Rates 6.1440G and Below
Table 9.  Default and Recommended Analog Parameter Values

The table shows default and recommended analog parameters values:
Parameter Value
FGT TXEQ Post Tap 1, 1.0 step size 0
FGT TXEQ Main Tap 1.0 step size 35
FGT TXEQ Pre Tap 1, 1.0 step size 5
FGT TXEQ Pre Tap 2, 1.0 step size 0
FGT RX Onchip Termination RX_ONCHIP_TERMINATION_R_2 (100 ohms)
Enable FGT RX AC Couple ENABLE
Enable FGT VSR mode
  • VSR_MODE_LOW_LOSS (for CPRI rate 24Gbps only)
  • VSR_MODE_DISABLE (shown error if it’s not selected for CPRI rate below 24Gbps)
RXEQ VGA Gain 0 (Required only when CPRI rate is 6.1440Gbps and below)
RXEQ High Frequency Boost 0 (Required only when CPRI rate is 6.1440Gbps and below)
RXEQ DFE Data Tap1 0 (Required only when CPRI rate is 6.1440Gbps and below)
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