F-Tile CPRI PHY Intel® FPGA IP User Guide

ID 683284
Date 8/15/2024
Public

7. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.08.15 24.2 4.3.3
  • Added Analog Parameters
  • Corrected 2.4376G (8b/10b) to 2.4576G (8b/10b) in Parameters
2023.12.04 23.4 4.3.1

Added support for Intel Agilex 9 FPGAs. The first suppported Quartus Prime version is v23.2.

2023.12.04 23.4 4.3.1 Updated the Quartus version and IP version. Also updated the Release Information section.
2023.10.02 23.3 4.3.0 In the IP Parameter Settings section, added the Analog Parameters information.
2023.04.03 23.1  
  • Updated product family name to "Intel Agilex 7."
2023.02.03 22.4 4.1.0

Deterministic Latency: Instances of signal ethlphy_wa changed to eth_wa occurring in the table Delay Equations for 10G/12G/24G without RS-FEC Variants

2022.09.26 22.3 4.0.0
  • Added support for new reference clock (122.88 MHz).
    • Updated the following sections:
      • Supported Features
      • IP Parameter Settings
      • Required Clock Frequencies
  • Corrected register names in section: Calculation for 64b/66b Datapath.
2022.06.21 22.2 3.3.0 Added the hardware design example support for:
  • Intel Agilex I-Series FPGA Development Kit
  • Intel Agilex I-Series Transceiver-SoC Development Kit
2022.03.28 22.1 3.2.0
  • Removed support for ModelSim* SE simulator.
  • Added a new parameter: Enable CDR Clock Output.
  • Updated the Required Clock Frequencies section.
2021.12.13 21.4 3.1.0
  • Added support for Xcelium* simulator.
  • Updated the Resource Utilization.
  • Added a new parameter: Enable Debug Endpoint for Datapath and PMA Avalon Memory-Mapped Interface.
2021.10.04 21.3 3.0.0
  • Added support for the following line rates:
    • 1.228 Gbps
    • 3.072 Gbps
    • 6.144 Gbps
  • Updated the following sections with new line rate information:
    • Supported Features
    • Resource Utilization
    • IP Parameter Settings
  • Updated the deterministic latency equations in section: Deterministic Latency.
  • Updated the address range for the IP Registers.
  • Added support for the following simulators:
    • Siemens* EDA QuestaSim* simulator
    • Questa* Intel® FPGA Edition simulator
2021.06.21 21.2 2.0.0 Initial release.