F-Tile CPRI PHY Intel® FPGA IP User Guide

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ID 683284
Date 8/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile CPRI PHY Intel® FPGA IP 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. IP Registers 6. F-Tile CPRI PHY Intel FPGA IP User Guide Archives 7. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide
1. About the F-Tile CPRI PHY Intel® FPGA IP x
1.1. Supported Features 1.2. Block Diagram 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. F-Tile CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
3. IP Parameter Settings x
3.1. Analog Parameters for F-Tile IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency 4.2.2. Calculation for 64b/66b Datapath
1. About the F-Tile CPRI PHY Intel® FPGA IP
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. IP Registers
6. F-Tile CPRI PHY Intel FPGA IP User Guide Archives
7. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

1.2. Block Diagram

The F-Tile CPRI PHY Intel® FPGA IP block diagram shows the main blocks, and internal and external connections for each variant.
Figure 1. IP Block Diagram
  • The RS-FEC block is optional for the IP core variations that target 10.1376, 12.1651, and 24.33024 Gbps CPRI line rate.
  • The soft reset controller implements the reset sequence of the IP core.
  • The IP variation with 1.2288, 2.4576, 3.072, 4.9152, 6.144, and 9.8304 Gbps CPRI line rate include 8b/10b soft PCS.
  • The IP variations that target CPRI line rates of 10.1376, 12.1651, and 24.33024 Gbps use 64b/66b hard PCS within the F-tile.
  • It supports latency measurement for delay calculation between the FPGA pins to the core.
Level Two Title