Visible to Intel only — GUID: mwh1409959687689
Ixiasoft
Visible to Intel only — GUID: mwh1409959687689
Ixiasoft
2.3.1. Using Standard Flow
Compiling all design partitions in a single Quartus® Prime project ensures that all design logic is compiled with a consistent set of assignments, and allows the software to perform global placement and routing optimizations. Compiling all design logic together is beneficial for FPGA design flows because all parts of the design must use the same shared set of device resources. Therefore, it is often easier to ensure good quality of results when partitions are developed within a single top-level Quartus® Prime project.