Visible to Intel only — GUID: mwh1409959783332
Ixiasoft
Visible to Intel only — GUID: mwh1409959783332
Ixiasoft
2.7. Including SDC Constraints from Lower-Level Partitions for Third-Party IP Delivery
Passing additional timing constraints from a partition to the top-level design must be managed carefully. You can design within a single Quartus® Prime project or a copy of the top-level design to simplify constraint management.
To ensure that there are no conflicts between the project lead’s top-level constraints and those added by the third-party IP designer, use two .sdc files for each separate Quartus® Prime project: an .sdc created by the project lead that includes project-wide constraints, and an .sdc created by the IP designer that includes partition-specific constraints.
The example design shown in the figure below is used to illustrate recommendations for managing the timing constraints in a third-party IP delivery flow. The top-level design instantiates a lower-level design block called module_A that is set as a design partition and developed by an IP designer in a separate Quartus® Prime project.
In this top-level design, there is a single clock setting called clk associated with the FPGA input called top_level_clk. The top-level .sdc contains the following constraint for the clock:
create_clock -name {clk} -period 3.000 -waveform { 0.000 1.500 } \ [get_ports {TOP_LEVEL_CLK}]