Visible to Intel only — GUID: mwh1409959801425
Ixiasoft
Visible to Intel only — GUID: mwh1409959801425
Ixiasoft
2.9.3. How to Size and Place Regions
In a late floorplan, when the design is complete, you can use locations or regions chosen by the Fitter as a guideline. If you have compiled the full design, you can view the location of the partition logic in the Chip Planner. You can use the natural grouping of each unconstrained partition as a starting point for a LogicLock region constraint. View the placement for each partition that requires a floorplan constraint, and create a new LogicLock region by drawing a box around the area on the floorplan, and then assigning the partition to the region to constrain the partition placement.
Instead of creating regions based on the previous compilation results, you can start with the Fitter results for a default auto size and floating origin location for each new region when the design logic is complete. After compilation, lock the size and origin location.
Alternatively, if the design logic is complete with auto-sized or floating location regions, you can specify the size based on the synthesis results and use the locations chosen by the Fitter with the Set to Estimated Size command. Like the previous option, start with floating origin location. After compilation, lock the origin location. You can also enable the Fast Synthesis Effort setting to reduce synthesis time.
After a compilation, save the Fitter size and origin location of the Fitter with the Set Size and Origin to Previous Fitter Results command.