Visible to Intel only — GUID: mwh1409959770016
Ixiasoft
Visible to Intel only — GUID: mwh1409959770016
Ixiasoft
2.5.4.5. Drive Clocks Directly
Connecting the clock signal directly avoids any timing analysis difficulties with gated clocks. Clock gating is never recommended for FPGA designs because of potential glitches and clock skew. Clock gating can be especially problematic with exported partitions because the partitions have no information about gating that takes place at the top-level design or in another partition. If a gated clock is required in a partition, perform the gating within that partition.
Direct connections to input clock pins also allows design partition scripts to send constraints from the top-level device pin to lower-level partitions.