Visible to Intel only — GUID: mwh1409959766720
Ixiasoft
Visible to Intel only — GUID: mwh1409959766720
Ixiasoft
2.5.4.1. Allocate Logic Resources
You can constrain logic utilization for the IP core using design floorplan location assignments. The design should specify I/O pin locations with pin assignments.
You can also specify limits for Quartus® Prime synthesis to allocate and balance resources. This procedure can also help if device resources are overused in the individual partitions during synthesis.
In the standard synthesis flow, the Quartus® Prime software can perform automated resource balancing for DSP blocks or RAM blocks and convert some of the logic into regular logic cells to prevent overuse.
You can use the Quartus® Prime synthesis options to control inference of IP cores that use the DSP, or RAM blocks. You can also use the IP Catalog and Parameter Editor to customize your RAM or DSP IP cores to use regular logic instead of the dedicated hardware blocks.