F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

Download PDF
ID 683281
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

2.2.4. Avalon® Memory-Mapped Decoder

The Avalon® memory-mapped decoder is an address decoder used to arbitrate multiple Avalon® memory-mapped interface agents to one Avalon® memory-mapped interface host. It is a scalable decoder that can support different number of agents, capable of partial or full address decoding.
Table 20.  Avalon Memory-Mapped Decoder Parameter
Parameter Name Default Value Description
SLAVE_NUM 3 Number of agent interfaces.
ADDR_WIDTH 32 Determines the width of master_addr and slave_addr.
DATA_WIDTH 32 Determines the width of master_writedata, master_readdata, slave_writedata, and slave_readdata.
BYTE_EN_WIDTH 4 Determines the width of master_byteenable and slave_byteenable.
PARTIAL_DECODING_EN 0
To enable partial decoding of address:
  • 0 – disabled (full decoding)
  • 1 – enabled
SLAVE_ADDR_SEL_LSB_INDEX 20 When partial decoding is enabled, specify the lower boundary of the agent address bit index to decode.
SLAVE_ADDR_SEL_MSB_INDEX 23 When partial decoding is enabled, specify the upper boundary of the agent address bit index to decode. Must be greater than or equal to SLAVE_ADDR_SEL_LSB_INDEX and must not exceed ADDR_WIDTH-1.
Table 21.  Avalon Memory-Mapped Decoder Ports
Port Name Width Direction Domain Description
clk 1 Input - Clock. Supply with i_reconfig_clk.
rst 1 Input clk Synchronous reset. Active high.
master_addr ADDR_WIDTH Input clk Avalon memory-mapped host address.
master_read 1 Input clk Avalon memory-mapped host read.
master_write 1 Input clk Avalon memory-mapped host write.
master_writedata DATA_WIDTH Input clk Avalon memory-mapped host write data.
master_byteenable BYTE_EN_WIDTH Input clk Avalon memory-mapped host byte enable.
master_readdata DATA_WIDTH Output clk Avalon memory-mapped host read data.
master_readdatavalid 1 Output clk Avalon memory-mapped host read data valid.
master_waitrequest 1 Output clk Avalon memory-mapped host wait request.
slave_addr ADDR_WIDTH Output clk Avalon memory-mapped agent address.
slave_writedata DATA_WIDTH Output clk Avalon memory-mapped agent write data.
slave_byteenable BYTE_EN_WIDTH Output clk Avalon memory-mapped agent byte enable.
slave_read SLAVE_NUM Output clk Avalon memory-mapped agent read.
slave_write SLAVE_NUM Output clk Avalon memory-mapped agent write.
slave_readdata SLAVE_NUM*DATA_WIDTH Input clk Avalon memory-mapped agent read data.
slave_readdatavalid SLAVE_NUM Input clk Avalon memory-mapped agent read data valid.
slave_waitrequest SLAVE_NUM Input clk Avalon memory-mapped agent wait request.
Level Two Title