F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 12/13/2021
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

1.6. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Intel® Agilex™ device, follow these steps:

  1. Ensure that hardware design example generation is complete.
  2. In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project <design_example_dir>/hardware_test_design/cpriphy_ftile_hw.qpf.
  3. Edit the .qsf file to assign pins based on your hardware.
  4. Click Processing > Start Compilation.
  5. After successful compilation, a .sof file is available in <design_example_dir>/hardware_test_design/output_files directory. Follow these steps to program the hardware design example on the Intel® Agilex™ device:
    1. Connect the Intel® Agilex™ I-series Transceiver Signal Integrity Development Kit to the host computer.
      Note: The development kit is preprogrammed with the correct clock frequencies by default. You do not need to use the Clock Control application to set the frequencies.
    2. Click Tools > Programmer > Hardware Setup.

    4. Select a programming device.
    5. Ensure that Mode is set to JTAG.
    6. Select the Intel® Agilex™ device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    7. In the row with your .sof, check the box for the .sof.
    8. Check the box in the Program/Configure column.
    9. Click Start.
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