AN 494: GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series

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ID 683261
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series
1. GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series x
1.1. GPIO Pin Expansion and I2C 1.2. I2C Interface for GPIO Pin Expansion 1.3. GPIO Pin Expansion Using I2C Bus Interface Using MAX II Devices 1.4. Acknowledgments 1.5. Document Revision History
1.2. I2C Interface for GPIO Pin Expansion x
1.2.1. I2C Interface 1.2.2. GPIO Interface
1.3. GPIO Pin Expansion Using I2C Bus Interface Using MAX II Devices x
1.3.1. Design Demonstration on the MDN-B2 Demo Board
1. GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series

1.2. I2C Interface for GPIO Pin Expansion

The supported Altera device acts as a slave on the I2C bus and has two pins on its I2C interface: the I2C clock SCL and the I2C data line SDA. The host system, which acts as an I2C master, communicates with the device (which acts as an I2C slave). The device presents eight general purpose input ports and eight general purpose output ports to the host. Data, which is transmitted serially over the I2C bus, is received in parallel at the GPIO pins. This way, all eight general purpose I/Os can be read or written at the same time.


Section Content
I2C Interface
GPIO Interface

Level Two Title