AN 494: GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series

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ID 683261
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series
1. GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series x
1.1. GPIO Pin Expansion and I2C 1.2. I2C Interface for GPIO Pin Expansion 1.3. GPIO Pin Expansion Using I2C Bus Interface Using MAX II Devices 1.4. Acknowledgments 1.5. Document Revision History
1.2. I2C Interface for GPIO Pin Expansion x
1.2.1. I2C Interface 1.2.2. GPIO Interface
1.3. GPIO Pin Expansion Using I2C Bus Interface Using MAX II Devices x
1.3.1. Design Demonstration on the MDN-B2 Demo Board
1. GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series

1.4. Acknowledgments

Design example adapted for Altera MAX 10 FPGAs by:

Orchid Technologies Engineering and Consulting, Inc.

Maynard, Massachusetts 01754

TEL: 978-461-2000

WEB: www.orchid-tech.com

EMAIL: info@orchid-tech.com

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