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1. 25G Ethernet Intel® FPGA IP Quick Start Guide
2. 10G/25G Ethernet Single-Channel Design Example for Stratix® 10 Devices
3. 25G Ethernet Single-Channel Design Example for Stratix® 10 Devices
4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices
5. 25G Ethernet Intel® FPGA IP Design Example References
6. 25G Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
7. Document Revision History for the 25G Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide
1.1. Directory Structure
1.2. Generating the Design Example
1.3. Simulating the 25G Ethernet Intel® FPGA IP Design Example Testbench
1.4. Compiling and Configuring the Design Example in Hardware
1.5. Changing Target Device in Hardware Design Example
1.6. Testing the 25G Ethernet Intel® FPGA IP Design in Hardware
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3.1. Features
- Supports single Ethernet channel operating at 25G.
- Generates design example with IEEE 1588v2 feature.
- Generates design example with RS-FEC feature.
- Generates design example separately from Stratix® 10 Transceiver Native PHY.
- Provides testbench and simulation script.