CIC Intel® FPGA IP: User Guide

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ID 683246
Date 9/30/2019
Public
Document Table of Contents
Document Table of Contents x
1. About the CIC Intel® FPGA IP 2. CIC Intel® FPGA IP Getting Started 3. CIC Intel® FPGA IP Functional Description 4. CIC Intel® FPGA IP User Guide Document Archives 5. CIC Intel® FPGA IP User Guide Document Revision History
1. About the CIC Intel® FPGA IP x
1.1. DSP Intel® FPGA IP Features 1.2. CIC Intel® FPGA IP Features 1.3. DSP Intel® FPGA IP Device Family Support 1.4. DSP Intel® FPGA IP Verification 1.5. CIC Intel® FPGA IP Release Information 1.6. CIC Intel® FPGA IP Performance and Resource Utilization
2. CIC Intel® FPGA IP Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. CIC IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. CIC Intel® FPGA IP Functional Description x
3.1. Variable Rate Change Factors 3.2. Multichannel Support 3.3. CIC Output Options 3.4. FIR Filter Compensation Coefficients 3.5. CIC Intel® FPGA IP Parameters 3.6. CIC Intel® FPGA IP Interfaces and Signals
3.2. Multichannel Support x
3.2.1. Multiple Input Single Output (MISO) 3.2.2. Single Input Multiple Output (SIMO)
3.3. CIC Output Options x
3.3.1. Output Data Width 3.3.2. Output Rounding 3.3.3. Hogenauer Pruning
3.6. CIC Intel® FPGA IP Interfaces and Signals x
3.6.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 3.6.2. CIC Intel® FPGA IP Signals 3.6.3. Avalon Streaming Interface Data Transfer Timing 3.6.4. Packet Data Transfers
1. About the CIC Intel® FPGA IP
2. CIC Intel® FPGA IP Getting Started
3. CIC Intel® FPGA IP Functional Description
4. CIC Intel® FPGA IP User Guide Document Archives
5. CIC Intel® FPGA IP User Guide Document Revision History

1.6. CIC Intel® FPGA IP Performance and Resource Utilization

The following parameters apply:
  • Number of stages: 8
  • Rate change factor: 8
  • Differential delay: 1
  • Integrator data storage: Memory (whenever possible)
  • Differentiator data storage: Memory (whenever possible)
  • Input data width: 16
  • Output data width: Full precision
  • Output rounding: No rounding

The target fMAX is 1 GHz.

Table 3.  CIC IP Core PerformanceTypical performance using the Quartus II software v14.1 with the Arria V (5AGXFB3H4F40C4), Cyclone V (5CGXFC7D6F31C6), and Stratix V (5SGSMD4H2F35C2) devices
Device Filter Type ALM Memory Registers fMAX (MHz)
M10K M20K Primary Secondary
Arria V Decimator 493 2 -- 1,149 5 207.34
Arria V Decimator 5 Channels 1,162 2 -- 3,749 6 207
Arria V Decimator 5 Channels 3 Interfaces 911 37 -- 1,722 6 255
Arria V Decimator Hogenauer Pruning 352 1 -- 785 12 304
Arria V Decimator Trunction 463 2 -- 1,055 5 198.69
Arria V Decimator Variable Rate Change 919 37 -- 1,730 7 256
Arria V Interpolator 326 1 -- 728 18 320
Arria V Interpolator 5 Channels 762 1 -- 2,369 27 288
Arria V Interpolator 5 Channels 3 Interfaces 886 27 -- 1,776 17 232.61
Arria V Interpolator Convergent Rounding 352 1 -- 785 12 304
Arria V Interpolator Variable Rate Change 889 27 -- 1,772 23 235
Cyclone V Decimator 492 2 -- 1,137 17 182
Cyclone V Decimator 5 Channels 1,162 2 -- 3,748 8 190.15
Cyclone V Decimator 5 Channels 3 Interfaces 906 37 -- 1,719 9 204
Cyclone V Decimator Hogenauer Pruning 352 1 -- 784 14 246
Cyclone V Decimator Truncation 463 2 -- 1,054 4 177
Cyclone V Decimator Variable Rate Change 917 37 -- 1,730 5 193.27
Cyclone V Interpolator 324 1 -- 709 37 264
Cyclone V Interpolator 5 Channels 760 1 -- 2,383 11 235
Cyclone V Interpolator 5 Channels 3 Interfaces 890 27 -- 1,747 48 168
Cyclone V Interpolator Convergent Rounding 352 1 -- 784 14 246.06
Cyclone V Interpolator Variable Rate Change 894 27 -- 1,725 70 165
Stratix V Decimator 515 -- 1 1,152 6 377
Stratix V Decimator 5 Channels 1,176 -- 1 3,750 8 413
Stratix V Decimator 5 Channels 3 Interfaces 1,891 -- 11 5,562 8 450.05
Stratix V Decimator Hogenauer Pruning 361 -- 0 790 13 450
Stratix V Decimator Truncation 483 -- 1 1,059 4 376
Stratix V Decimator Variable Rate Change 1,900 -- 11 5,574 3 450
Stratix V Interpolator 335 -- 0 737 14 450.05
Stratix V Interpolator 5 Channels 771 -- 0 2,390 8 450
Stratix V Interpolator 5 Channels 3 Interfaces 1,625 -- 8 4,635 70 450
Stratix V Interpolator Convergent Rounding 361 -- 0 790 13 450
Arria 10 Interpolator Variable Rate Change 464 -- 0 128 128 451
Level Two Title