Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

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ID 683243
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Timing Analysis Introduction 3. Using the Intel® Quartus® Prime Timing Analyzer A. Intel® Quartus® Prime Pro Edition User Guides
2. Timing Analysis Introduction x
2.1. What's New In This Version 2.2. Timing Analysis Basic Concepts 2.3. Timing Analysis Overview Document Revision History
2.2. Timing Analysis Basic Concepts x
2.2.1. Timing Path and Clock Analysis 2.2.2. Clock Setup Analysis 2.2.3. Clock Hold Analysis 2.2.4. Recovery and Removal Analysis 2.2.5. Multicycle Path Analysis 2.2.6. Metastability Analysis 2.2.7. Timing Pessimism 2.2.8. Clock-As-Data Analysis 2.2.9. Multicorner Timing Analysis 2.2.10. Time Borrowing
2.2.1. Timing Path and Clock Analysis x
2.2.1.1. The Timing Netlist 2.2.1.2. Timing Paths 2.2.1.3. Data and Clock Arrival Times 2.2.1.4. Launch and Latch Edges
2.2.5. Multicycle Path Analysis x
2.2.5.1. Multicycle Clock Hold 2.2.5.2. Multicycle Clock Setup
2.2.10. Time Borrowing x
2.2.10.1. Time Borrowing Limitations 2.2.10.2. Time Borrowing with Latches
3. Using the Intel® Quartus® Prime Timing Analyzer x
3.1. Timing Analysis Flow 3.2. Step 1: Specify Timing Analyzer Settings 3.3. Step 2: Specify Timing Constraints 3.4. Step 3: Run the Timing Analyzer 3.5. Step 4: Analyze Timing Reports 3.6. Applying Timing Constraints 3.7. Timing Analyzer Tcl Commands 3.8. Timing Analysis of Imported Compilation Results 3.9. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History 3.10. Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
3.4. Step 3: Run the Timing Analyzer x
3.4.1. Setting the Operating Conditions for Timing Analysis 3.4.2. Enabling Time Borrowing Optimization 3.4.3. Promoting Critical Warnings to Errors
3.5. Step 4: Analyze Timing Reports x
3.5.1. Generating Timing Reports 3.5.2. Cross-Probing with Design Assistant 3.5.3. Launching Design Assistant from Timing Analyzer 3.5.4. Locating Timing Paths in Other Tools 3.5.5. Correlating Constraints to the Timing Report
3.5.1. Generating Timing Reports x
3.5.1.1. Report Fmax Summary 3.5.1.2. Report Timing 3.5.1.3. Report Timing By Source Files 3.5.1.4. Report Data Delay 3.5.1.5. Report Net Delay 3.5.1.6. Report Clocks and Clock Network 3.5.1.7. Report Clock Transfers 3.5.1.8. Report Metastability 3.5.1.9. Report CDC Viewer 3.5.1.10. Report Asynchronous CDC 3.5.1.11. Report Logic Depth 3.5.1.12. Report Neighbor Paths 3.5.1.13. Report Register Spread 3.5.1.14. Report Route Net of Interest 3.5.1.15. Report Retiming Restrictions 3.5.1.16. Report Register Statistics 3.5.1.17. Report Pipelining Information 3.5.1.18. Report Time Borrowing Data 3.5.1.19. Report Exceptions and Exceptions Reachability 3.5.1.20. Report Bottlenecks
3.5.1.13. Report Register Spread x
3.5.1.13.1. Registers with High Timing Path Endpoint Tension 3.5.1.13.2. Registers with High Immediate Fan-Out Tension
3.5.1.20. Report Bottlenecks x
3.5.1.20.1. Specifying Custom Bottleneck Criteria
3.5.2. Cross-Probing with Design Assistant x
3.5.2.1. Cross-Probing from Design Assistant to Timing Analyzer
3.6. Applying Timing Constraints x
3.6.1. Recommended Initial SDC Constraints 3.6.2. SDC File Precedence 3.6.3. Modifying Iterative Constraints 3.6.4. Using Entity-bound SDC Files 3.6.5. Creating Clocks and Clock Constraints 3.6.6. Creating I/O Constraints 3.6.7. Creating Delay and Skew Constraints 3.6.8. Creating Timing Exceptions 3.6.9. Using Fitter Overconstraints 3.6.10. Example Circuit and SDC File
3.6.1. Recommended Initial SDC Constraints x
3.6.1.1. Create Clock (create_clock) 3.6.1.2. Derive PLL Clocks (derive_pll_clocks) 3.6.1.3. Derive Clock Uncertainty (derive_clock_uncertainty) 3.6.1.4. Set Clock Groups (set_clock_groups)
3.6.4. Using Entity-bound SDC Files x
3.6.4.1. Entity-bound Constraint Scope 3.6.4.2. Entity-bound Constraint Examples
3.6.5. Creating Clocks and Clock Constraints x
3.6.5.1. Creating Base Clocks 3.6.5.2. Creating Virtual Clocks 3.6.5.3. Creating Generated Clocks (create_generated_clock) 3.6.5.4. Deriving PLL Clocks 3.6.5.5. Creating Clock Groups (set_clock_groups) 3.6.5.6. Accounting for Clock Effect Characteristics 3.6.5.7. Constraining CDC Paths
3.6.5.1. Creating Base Clocks x
3.6.5.1.1. Automatic Clock Detection and Constraint Creation
3.6.5.2. Creating Virtual Clocks x
3.6.5.2.1. Specifying I/O Interface Uncertainty 3.6.5.2.2. I/O Interface Clock Uncertainty Example
3.6.5.3. Creating Generated Clocks (create_generated_clock) x
3.6.5.3.1. Clock Divider Example (-divide_by) 3.6.5.3.2. Clock Multiplexer Example
3.6.5.5. Creating Clock Groups (set_clock_groups) x
3.6.5.5.1. Exclusive Clock Groups (-logically_exclusive or -physically_exclusive) 3.6.5.5.2. Asynchronous Clock Groups (-asynchronous) 3.6.5.5.3. set_clock_groups Constraint Tips
3.6.5.6. Accounting for Clock Effect Characteristics x
3.6.5.6.1. Set Clock Latency (set_clock_latency) 3.6.5.6.2. Clock Uncertainty
3.6.6. Creating I/O Constraints x
3.6.6.1. Input Constraints (set_input_delay) 3.6.6.2. Output Constraints (set_output_delay)
3.6.7. Creating Delay and Skew Constraints x
3.6.7.1. Advanced I/O Timing and Board Trace Model Delay 3.6.7.2. Maximum Skew (set_max_skew) 3.6.7.3. Net Delay (set_net_delay)
3.6.8. Creating Timing Exceptions x
3.6.8.1. Timing Exception Precedence 3.6.8.2. False Paths (set_false_path) 3.6.8.3. Minimum and Maximum Delays 3.6.8.4. Multicycle Paths 3.6.8.5. Multicycle Exception Examples 3.6.8.6. Delay Annotation 3.6.8.7. Constraining Design Partition Ports
3.6.8.4. Multicycle Paths x
3.6.8.4.1. Common Multicycle Applications 3.6.8.4.2. Relaxing Setup with Multicycle (set_multicyle_path) 3.6.8.4.3. Accounting for a Phase Shift (-phase)
3.6.8.5. Multicycle Exception Examples x
3.6.8.5.1. Default Multicycle Analysis 3.6.8.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0 3.6.8.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1 3.6.8.5.4. Same Frequency Clocks with Destination Clock Offset 3.6.8.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency 3.6.8.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset 3.6.8.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency 3.6.8.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
3.7. Timing Analyzer Tcl Commands x
3.7.1. The quartus_sta Executable 3.7.2. Collection Commands
3.7.2. Collection Commands x
3.7.2.1. Wildcard Characters 3.7.2.2. Adding and Removing Collection Items 3.7.2.3. Query of Collections 3.7.2.4. Using the get_pins Command
1. Answers to Top FAQs
2. Timing Analysis Introduction
3. Using the Intel® Quartus® Prime Timing Analyzer
A. Intel® Quartus® Prime Pro Edition User Guides

3.9. Using the Intel® Quartus® Prime Timing Analyzer Document Revision History

Document Version Intel® Quartus® Prime Version Changes
2023.10.02 23.3
  • Updated compilation dashboard image in Step 3: Run the Timing Analyzer.
  • Revised the following topics entirely:
    • Using Entity-bound SDC Files
    • Entity-bound Constraint Scope
    • Entity-bound Constraint Examples
2023.08.03 23.1
  • Corrected typo in command example in Report Data Delay topic.
  • Corrected typo in command example in Constraining CDC Paths topic.
  • Corrected typo in command example in Maximum Skew topic.
  • Added Promoting Critical Warnings to Errors topic.
2023.04.03 23.1
  • Revised updated image and description in Report Register Description for new Without a Control Signal and Synchronous Load columns and data.
2023.01.31 22.4
  • Revised outdated timing model descriptions in Setting the Operating Conditions for Timing Analysis topic.
2022.09.26 22.3
  • Renamed the report title "Report Reset Statistics" as "Report Register Statistics."
  • Revised the Report Register Statistics topic to describe some new features of the report.
  • Revised Report Fmax Summary topic to refer to get_clock_fmax_info command and provide more detail.
  • Revised Example SDC Constraints for External Clock Mux to replace logically_exclusive with physically_exclusive.
2022.03.28 22.1
  • Described new Clock Network Viewer in Report Clocks and Clock Networks topic.
  • Updated Report Register Spread topic for new angle and area spread types and -to_clock filtering.
  • Added new Report Timing By Source Files topic.
  • Added new Report Metastability topic.
  • Added new Report Bottlenecks topic.
  • Added new Specifying Custom Bottleneck Criteria topic.
  • Revised Basic .sdc Constraints Example in Example Circuit and SDC File topic.
  • Added more detailed constraint example and diagram to Set Clock Groups topic.
  • Revised scripting examples and screenshots in Correlating Constraints to the Timing Report topic.
  • Revised scripting example in Creating Base Clocks topic.
  • Revised scripting example in Clock Divider Example topic.
  • Revised Constraining CDC Paths topic.
  • Added note about referenced SDCs within IP to SDC File Precedence topic.
2021.09.27 21.3
  • Updated name of Report Hierarchical Retiming Restrictions command and report to Report Retiming Restrictions.
  • Added Constraining CDC Paths topic and linked to related topics.
  • Updated Setting the Operating Conditions with details about operating condition nomenclature.
  • Replaced Custom Reports, Device Specific, Diagnostic, and Slack report folder names throughout.
  • Added Report Exceptions and Exceptions Reachability topic describing new report.
  • Added Report Clocks and Clock Networks topic describing new report.
  • Added Report Data Delay topic describing report.
  • Mentioned option to view multiple before and after paths in Report Neighbor Paths topic.
  • Added set_clock_groups to Timing Exception Precedence
  • Updated content of Extra Info tab in Report Timing topic.
  • Corrected the set_clock_groups -group A -group B table in the Creating Clock Groups topic.
  • Removed Report Custom CDC Viewer Command topic.
  • Revised assignment examples in Exclusive Clock Groups topic.
2021.04.05 21.1
  • Added:
    • "Report Reset Statistics"
    • "Report Asynchronous CDC"
    • Two new fields to "Report Pipelining Information".
    • New screenshots to "Report Logic Depth" and "Report Neighbor Paths"
    • get_registers and get_keepers to "Collection Commands".
  • Removed -include and -exclude options from "Maximum Skew"
2021.02.22 20.3 Added extra SDC_ENTITY_FILE info to "Using Entity-bound SDC Files"
2020.09.28 20.3
  • Added "Cross Probing with Design Assistant" section.
  • Updated “Step 3: Run the Timing Analyzer” for multiple methods.
  • Updated "Step 1: Specify Timing Analyzer Settings for new tabbed dialog box and options.
  • Added new "Report Register Spread," "Report Route Net of Interest," "Report Hierarchical Retiming Restrictions," and "Report Pipelining Information" topics.
  • Updated "Report Clock Transfers" topic for new data columns.
  • Updated "Report Timing" topic for Extra Info tab data.
  • Updated "Report Fmax Summary," "Report Logic Depth," "Report Neighbor Paths," "Report CDC Viewer," and "Report Custom CDC Viewer" topics for latest GUI and consistency.
2020.04.13 20.1
  • Added details and Intel Agilex® 7 device examples to "Setting the Operating Conditions" topic.
  • Added "Report Logic Level Depth" topic.
  • Added "Report Neighbor Paths" topic.
  • Added "Enabling Time Borrowing Optimization" topic.
  • Added "Report Time Borrowing Data" topic.
2019.07.15 19.2
  • Updated "Setting Operating Conditions" for SmartVID timing models.
  • Added step for setting operating conditions to "Step 4: Run Timing Analysis."
  • Added details about exclusive paths to "Maximum Skew" topic.
  • Added GUI steps for creating entity-bound SDC files to "Using Entity-bound SDC Files" topic.
2019.04.15 19.1
  • Corrected typo in "Timing Constraint Precedence" topic.
  • Corrected typo in "Maximum Skew" topic.
  • Updated "Viewing Design Assistant Recommendations" for latest GUI changes.
2018.11.07 18.1
  • Improved description and diagram for "Exclusive Clock Groups" topic.
2018.09.24 18.1
  • Added "Using Entity-bound SDC Files" topic.
  • Added "Scoping Entity-bound Constraints" topic.
  • Added "Entity-bound Constraint Examples" topic.
  • Revised "Basic Timing Analysis Flow" section to add sequential step organization, update steps, and add supporting screenshots.
  • Added Timing Analyzer screenshot to "Using the Timing Analyzer" topic.
  • Removed "Creating a Constraint File from Templates with the Text Editor" topic due to limitations of this feature in this version of the software.
  • Retitled "SDC Constraint Creation Summary" to " Dual Clock SDC Example."
  • Retitled "Default Settings" to "Default Multicycle Analysis."
  • Retitled "SDC (Clock and Exception) Assignments on Blackbox Ports" to "Constraining Design Partition Ports."
  • Added "Viewing Design Assistant Recommendations" topic.
2018.05.07 18.0
  • First release as part of the stand-alone Timing Analyzer User Guide
2017.11.27 17.1.0
  • Removed outdated figure: Design Flow with the Timing Analyzer.
  • Updated Performing an Initial Analysis and Synthesis topic with Intel® Quartus® Prime Pro Edition commands.
2017.11.06 17.1
  • Updated Using Fitter Overconstraints topic for Intel® Stratix® 10 support.
2017.05.08 17.0
  • Added Using Fitter Overconstraints topic.
  • Added Clock Domain Crossing report topics
2016.10.31 16.1
  • Implemented Intel rebranding.
  • Added support for -blackbox option with set_input_delay, set_output_delay, remove_input_delay, remove_output_delay.
2016.05.03 16.0 Added new topic: SCDS (Clock and Exception) Assignments on Blackbox Ports
2015.11.02 15.1.0
  • Changed instances of Quartus II to Quartus Prime.
  • Added a description of running three- and four-corner analysis with --mode=implement|finalize.
  • Added description for new set_operating_conditions UI.
2015.05.04 15.0.0 Added and updated contents in support of new timing algorithms for Arria 10:
  • Enhanced Timing Analysis for Arria 10
  • Maximum Skew (set_max_skew command)
  • Net Delay (set_net_delay command)
  • Create Generated Clocks (clock-as-data example)
2014.12.15 14.1 Major reorganization. Revised and added content to the following topic areas:
  • Timing Constraints
  • Create Clocks and Clock Constraints
  • Creating Generated Clocks
  • Creating Clock Groups
  • Clock Uncertainty
  • Running the Timing Analyzer
  • Generating Timing Reports
  • Understanding Results
  • Constraining and Analyzing with Tcl Commands
August 2014 14.0a10.0 Added command line compilation requirements for Arria 10 devices.
June 2014 14.0
  • Minor updates.
  • Updated format.
November 2013 13.1
  • Removed HardCopy device information.
June 2012 12.0
  • Reorganized chapter.
  • Added “Creating a Constraint File from Intel® Quartus® Prime Templates with the Intel® Quartus® Prime Text Editor” section on creating an SDC constraints file with the Insert Template dialog box.
  • Added “Identifying the Intel® Quartus® Prime Software Executable from the SDC File” section.
  • Revised multicycle exceptions section.
November 2011 11.1
  • Consolidated content from the Best Practices for the Intel® Quartus® Prime Timing Analyzer chapter.
  • Changed to new document template.
May 2011 11.0
  • Updated to improve flow. Minor editorial updates.
December 2010 10.1
  • Changed to new document template.
  • Revised and reorganized entire chapter.
  • Linked to Intel® Quartus® Prime Help.
July 2010 10.0 Updated to link to content on SDC commands and the Timing Analyzer GUI in Intel® Quartus® Prime Help.
November 2009 9.1 Updated for the Intel® Quartus® Prime software version 9.1, including:
  • Added information about commands for adding and removing items from collections
  • Added information about the set_timing_derate and report_skew commands
  • Added information about worst-case timing reporting
  • Minor editorial updates
November 2008 8.1 Updated for the Intel® Quartus® Prime software version 8.1, including:
  • Added the following sections:

    “set_net_delay” on page 7–42

    “Annotated Delay” on page 7–49

    “report_net_delay” on page 7–66

  • Updated the descriptions of the -append and -file < name > options in tables throughout the chapter
  • Updated entire chapter using 8½” × 11” chapter template
  • Minor editorial updates
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