Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 10/02/2023
Public

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3.6.7.2. Maximum Skew (set_max_skew)

The Set Max Skew (set_max_skew) constraint specifies the maximum allowable skew between the sets of registers or ports you specify. In order to constrain skew across multiple paths, you must constrain all such paths within a single set_max_skew constraint.
set_max_skew -from_clock { clock } -to_clock { * } -from foo -to blat 2

The set_max_delay, set_min_delay, and set_multicycle_path constraints do not affect the set_max_skew timing constraint. However, the set_clock_groups constraint does impact the set_max_skew constraint.

Note: Exclusive clock groups (set with set_clock_groups -exclusive) override set_max_skew constraints.

The Timing Analyzer does not compare two paths for skew if their clocks are exclusive to each other. However, the Timing Analyzer does analyze for skew paths whose clocks are asynchronous.

Table 29.  set_max_skew Options
Arguments Description
-h | -help Short help.
-long_help Long help with examples and possible return values.
-fall_from_clock <names> Valid source clocks (Tcl matches string patterns). Analysis only considers paths from falling clock edges.
-fall_to_clock <names> Valid destination clocks (Tcl matches string patterns). Analysis only considers paths from falling clock edges.
-from <names> 3 Valid sources (Tcl matches string patterns).
-from_clock <names> Valid source clocks (Tcl matches string patterns).
-get_skew_value_from_clock_period <src_clock_period|dst_clock_period|min_clock_period> Option to interpret skew constraint as a multiple of the clock period.
-rise_from_clock <names> Valid source clocks (Tcl matches string patterns). Analysis only considers paths from rising clock edges.
-rise_to_clock <names> Valid destination clocks (Tcl matches string patterns). Analysis only considers paths to rising clock edges.
-skew_value_multiplier <multiplier> Value by which the clock period multiplies to compute skew requirement.
-to <names> 3 Valid destinations (Tcl matches string patterns)
-to_clock <names> Valid destination clocks (Tcl matches string patterns).
<skew> The value of the skew you require.

Applying maximum skew constraints between clocks applies the constraint from all register or ports driven by the clock you specify (with the -from option) to all registers or ports driven by the clock you specify (with the -to option).

Maximum skew analysis can include data arrival times, clock arrival times, register micro parameters, clock uncertainty, on-die variation, and clock pessimism removal. Among these, the Fitter only disables clock pessimism removal by default.

Use -get_skew_value_from_clock_period to set the skew as a multiple of the launching or latching clock period, or whichever of the two has a smaller period. If you use this option, set -skew_value_multiplier, and you may not set the positional skew option. If more than one clock clocks the set of skew paths, Timing Analyzer uses the clock with smallest period to compute the skew constraint.

Click Report Max Skew... (report_max_skew) to view the max skew analysis. Since skew occurs between two or more paths, no results display if the -from/-from_clock and -to/-to_clock filters satisfy less than two paths.

3 Legal values for the -from and -to options are collections of clocks, registers, ports, pins, cells or partitions in a design.