Visible to Intel only — GUID: vgo1440400733939
Ixiasoft
Visible to Intel only — GUID: vgo1440400733939
Ixiasoft
3.3.2. Mixed-Port Read-During-Write Mode
Output Mode | Memory Type | Description | Supported Operation Mode |
---|---|---|---|
New Data | MLAB | A read-during-write operation to different ports causes the MLAB registered output to reflect the New Data on the next rising edge after the data is written to the MLAB memory. This mode is available only if the output is registered. |
|
Old Data | M20K, MLAB | A read-during-write operation to different ports causes the RAM output to reflect the Old Data value at that particular address. For MLAB, this mode is available only if the output is registered. |
|
Don't Care | M20K, MLAB | The RAM produces Don't Care or Unknown value.
|
|
New_a_old_b | M20K | The read-during-write operation to different ports causes the RAM output to reflect new data at port A and old data at port B. |
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RAM: 2-PORT Intel® FPGA IP Settings | Output Behavior | |||
---|---|---|---|---|
Parameter | Enabled Parameter Options | altera_syncram Parameter (read_during_write_mode_mixed_ ports) |
Output Data when Read-During-Write | MLAB Atom (visible in Chip Planner) |
Mixed Port Read-During-Write for Single Input Clock RAM How should the q_a and q_b outputs behave when reading a memory location that is being written from the other ports? |
Old Data | old_data | Old data 4 | New Data |
New Data | new_data | New data | New Data | |
Don't Care | dont_care | Don't care 5 | Don't Care |