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1. Intel® Agilex™ Embedded Memory Overview
2. Intel® Agilex™ Embedded Memory Architecture and Features
3. Intel® Agilex™ Embedded Memory Design Considerations
4. Intel® Agilex™ Embedded Memory IP References
5. Intel® Agilex™ Embedded Memory Debugging
6. Intel® Agilex™ Embedded Memory User Guide Archives
7. Document Revision History for the Intel® Agilex™ Embedded Memory User Guide
2.1. Byte Enable in Intel® Agilex™ Embedded Memory Blocks
2.2. Address Clock Enable Support
2.3. Asynchronous Clear and Synchronous Clear
2.4. Memory Blocks Error Correction Code (ECC) Support
2.5. Intel® Agilex™ Embedded Memory Clocking Modes
2.6. Intel® Agilex™ Embedded Memory Configurations
2.7. Force-to-Zero
2.8. Coherent Read Memory
2.9. Freeze Logic
2.10. True Dual Port Dual Clock Emulator
2.11. Initial Value of Read and Write Address Registers
2.12. Timing/Power Optimization Feature in M20K Blocks
2.13. Intel® Agilex™ Supported Embedded Memory IPs
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Read Behavior
3.3. Customize Read-During-Write Behavior
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Advanced Settings in Intel® Quartus® Prime Software for Memory
3.9. Consider the Memory Depth Setting
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs
4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters
4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters
4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters
4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters
4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters
4.1.7. Changing Parameter Settings Manually
4.1.8. RAM and ROM Interface Signals
4.3.1. Release Information for FIFO Intel® FPGA IP
4.3.2. Configuration Methods
4.3.3. Specifications
4.3.4. FIFO Functional Timing Requirements
4.3.5. SCFIFO ALMOST_EMPTY Functional Timing
4.3.6. FIFO Output Status Flag and Latency
4.3.7. FIFO Metastability Protection and Related Options
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.3.9. SCFIFO and DCFIFO Show-Ahead Mode
4.3.10. Different Input and Output Width
4.3.11. DCFIFO Timing Constraint Setting
4.3.12. Coding Example for Manual Instantiation
4.3.13. Design Example
4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing
4.3.15. Guidelines for Embedded Memory ECC Feature
4.3.16. FIFO Intel® FPGA IP Parameters
4.3.17. Reset Scheme
4.4.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP
4.4.2. Shift Register (RAM-based) Intel® FPGA IP Features
4.4.3. Shift Register (RAM-based) Intel® FPGA IP General Description
4.4.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings
4.4.5. Shift Register Ports and Parameters Setting
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4.3.6. FIFO Output Status Flag and Latency
The main concern in most FIFO design is the output latency of the read and write status signals.
Output Mode | Optimization Option 20 | Output Latency (in number of clock cycles) |
---|---|---|
Normal 21 | Speed | wrreq / rdreq to full: 1 |
wrreq to empty: 2 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
rdreq to q[]: 1 | ||
Area | wrreq / rdreq to full: 1 | |
wrreq / rdreq to empty : 1 | ||
wrreq / rdreq to usedw[] : 1 | ||
rdreq to q[]: 1 | ||
Show-ahead 21 | Speed | wrreq / rdreq to full: 1 |
wrreq to empty: 3 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
wrreq to q[]: 3 | ||
rdreq to q[]: 1 | ||
Area | wrreq / rdreq to full: 1 | |
wrreq to empty: 2 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
wrreq to q[]: 2 | ||
rdreq to q[]: 1 |
Output Mode | Optimization Option 22 | Output Latency (in number of clock cycles) |
---|---|---|
Normal 23 | Speed | wrreq / rdreq to full: 1 |
wrreq to empty: 1 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
rdreq to q[]: 1 | ||
Area | wrreq / rdreq to full: 1 | |
wrreq / rdreq to empty : 1 | ||
wrreq / rdreq to usedw[] : 1 | ||
rdreq to q[]: 1 | ||
Show-ahead 23 | Speed | wrreq / rdreq to full: 1 |
wrreq to empty: 1 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
wrreq to q[]: 1 | ||
rdreq to q[]: 1 | ||
Area | wrreq / rdreq to full: 1 | |
wrreq to empty: 1 | ||
rdreq to empty: 1 | ||
wrreq / rdreq to usedw[]: 1 | ||
wrreq to q[]: 1 | ||
rdreq to q[]: 1 |
Output Latency (in number of clock cycles) |
---|
wrreq to wrfull: 1 wrclk |
wrreq to rdfull: 2 wrclk cycles + following n rdclk 24 |
wrreq to wrempty: 1 wrclk |
wrreq to rdempty: 2 wrclk 25 + following n rdclk 25 |
wrreq to wrusedw[]: 2 wrclk |
wrreq to rdusedw[]: 2 wrclk + following n + 1 rdclk 25 |
wrreq to q[]: 1 wrclk + following 1 rdclk 25 |
rdreq to rdempty: 1 rdclk |
rdreq to wrempty: 1 rdclk + following n wrclk 25 |
rdreq to rfull: 1 rdclk |
rdreq to wrfull: 1 rdclk + following n wrclk 25 |
rdreq to rdusedw[]: 2 rdclk |
rdreq to wrusedw[]: 1 rdclk + following n + 1 wrclk 25 |
rdreq to q[]: 1 rdclk |
20 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER parameter to ON. Setting the parameter to OFF is equivalent to area optimization.
21 Normal output mode is equivalent to setting the LPM_SHOWAHEAD parameter to OFF. For Show-ahead mode, the parameter is set to ON.
22 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER parameter to ON. Setting the parameter to OFF is equivalent to area optimization.
23 Normal output mode is equivalent to setting the LPM_SHOWAHEAD parameter to OFF. For Show-ahead mode, the parameter is set to ON.
24 The number of n cycles for rdclk and wrclk is equivalent to the number of synchronization stages and are related to the WRSYNC_DELAYPIPE and RDSYNC_DELAYPIPE parameters. For more information about how the actual synchronization stage (n) is related to the parameters set for different target device, refer to FIFO Metastability Protection and Related Options .
25 This is applied only to Show-ahead output modes. Show-ahead output mode is equivalent to setting the LPM_SHOWAHEAD parameter to ON.