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Ixiasoft
Visible to Intel only — GUID: eis1414478232342
Ixiasoft
4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing
The following section shows an example of how large skew between the gray-code counter bits can corrupt the counter sequence. Taking a counter width with 3-bit wide and assuming it is transferred from write clock domain to read clock domain. Assume all the counter bits have 0 delay relative to the destination clock, excluding the bit[0] that has delay of 1 clock period of source clock. That is, the skew of the counter bits is 1 clock period of the source clock when they arrived at the destination registers.
The following shows the correct gray-code counter sequence:
000,
001,
011,
010,
110....
which then transfers the data to the read domain, and on to the destination bus registers.
Because of the skew for bit[0], the destination bus registers receive the following sequence:
000,
000,
011,
011,
110....
Because of the skew, a 2-bit transition occurs. This sequence is acceptable if the timing is met. If the 2-bit transition occurs and both bits violate timing, it may result in the counter bus settled at a future or previous counter value, which corrupts the DCFIFO.
Therefore, the skew must be within a certain skew to ensure that the sequence is not corrupted.