5.5. Signals
Signal | Type | Required | Description |
---|---|---|---|
data_a | Input | Optional | Data input to port A of the memory. The data_a port is required if you set the operation_mode parameter to any of the following values:
|
address_a | Input | Yes | Address input to port A of the memory. The address_a signal is required for all operation modes. |
wren_a | Input | Optional | Write enable input for address_a port. The wren_a signal is required if you set the operation_mode to any of the following values:
|
rden_a | Input | Optional | Read enable input for address_a port. The rden_a signal is supported depending on your selected memory mode and memory block. |
byteena_a | Input | Optional | Byte enable input to mask the data_a port so that only specific bytes, nibbles, or bits of the data are written. The byteena_a port is not supported in the following conditions:
|
addressstall_a | Input | Optional | Address clock enable input to hold the previous address of address_a port for as long as the addressstall_a port is high. |
q_a | Output | Yes | Data output from port A of the memory. The q_a port is required if the operation_mode parameter is set to any of the following values:
|
data_b | Input | Optional | Data input to port B of the memory. The data_b port is required if the operation_mode parameter is set to BIDIR_DUAL_PORT. |
address_b | Input | Optional | Address input to port B of the memory. The address_b port is required if the operation_mode parameter is set to the following values:
|
wren_b | Input | Yes | Write enable input for address_b port. The wren_b port is required if operation_mode is set to BIDIR_DUAL_PORT. |
rden_b | Input | Optional | Read enable input for address_b port. The rden_b port is supported depending on your selected memory mode and memory block |
byteena_b | Input | Optional | Byte enable input to mask the data_b port so that only specific bytes, nibbles, or bits of the data are written. The byteena_b port is not supported in the following conditions:
|
addressstall_b | Input | Optional | Address clock enable input to hold the previous address of address_b port for as long as the addressstall_b port is high. |
q_b | Output | Yes | Data output from port B of the memory. The q_b port is required if the operation_mode is set to the following values:
The width of q_b port must be equal to the width of data_b port. |
clock0 | Input | Yes | The following describes which of your memory clock must be connected to the clock0 port, and port synchronization in different clocking modes:
|
clock1 | Input | Optional | The following describes which of your memory clock must be connected to the clock1 port, and port synchronization in different clocking modes:
|
clocken0 | Input | Optional | Clock enable input for clock0 port. |
clocken1 | Input | Optional | Clock enable input for clock1 port. |
clocken2 | Input | Optional | Clock enable input for clock0 port. |
clocken3 | Input | Optional | Clock enable input for clock1 port. |
aclr0 aclr1 |
Input | Optional | Asynchronously clear the registered input and output ports. The aclr0 port affects the registered ports that are clocked by clock0 clock, while the aclr1 port affects the registered ports that are clocked by clock1 clock. The asynchronous clear effect on the registered ports can be controlled through their corresponding asynchronous clear parameter, such as outdata_aclr_a,address_aclr_a, and so on. |
eccstatus | Output | Optional | A 3-bit wide error correction status port. Indicate whether the data that is read from the memory has an error in single-bit with correction, fatal error with no correction, or no error bit occurs. In Stratix V devices, the M20K ECC status is communicated with two-bit wide error correction status port. The M20K ECC detects and fixes a single bit error event or a double adjacent error event, or detects three adjacent errors without fixing the errors. The eccstatus port is supported if all the following conditions are met:
|
data | Input | Yes | Data input to the memory. The data port is required and the width must be equal to the width of the q port. |
wraddress | Input | Yes | Write address input to the memory. The wraddress port is required and must be equal to the width of the raddress port. |
wren | Input | Yes | Write enable input for wraddress port. The wren port is required. |
rdaddress | Input | Yes | Read address input to the memory. The rdaddress port is required and must be equal to the width of wraddress port. |
rden | Input | Optional | Read enable input for rdaddress port. The rden port is supported when the use_eab parameter is set to OFF. The rden port is not supported when the ram_block_type parameter is set to MLAB. Instantiate the ALTSYNCRAM IP core if you want to use read enable feature with other memory blocks. |
byteena | Input | Optional | Byte enable input to mask the data port so that only specific bytes, nibbles, or bits of data are written. The byteena port is not supported when use_eab parameter is set to OFF. It is supported in Arria II GX and newer devices with the ram_block_type parameter set to MLAB. |
wraddressstall | Input | Optional | Write address clock enable input to hold the previous write address of wraddress port for as long as the wraddressstall port is high. |
rdaddressstall | Input | Optional | Read address clock enable input to hold the previous read address of rdaddress port for as long as the wraddressstall port is high. The rdaddressstall port is only supported in newer devices except when the rdaddress_reg parameter is set to UNREGISTERED. |
q | Output | Yes | Data output from the memory. The q port is required, and must be equal to the width data port. |
inclock | Input | Yes | The following describes which of your memory clock must be connected to the inclock port, and port synchronization in different clocking modes:
|
outclock | Input | Yes | The following describes which of your memory clock must be connected to the outclock port, and port synchronization in different clocking modes:
|
inclocken | Input | Optional | Clock enable input for inclock port. |
outclocken | Input | Optional | Clock enable input for outclock port. |
aclr | Input | Optional | Asynchronously clear the registered input and output ports. The asynchronous clear effect on the registered ports can be controlled through their corresponding asynchronous clear parameter, such as indata_aclr, wraddress_aclr, and so on. |