5.2. RAM: 2-Port IP Core Parameters
Parameter | Legal Values | Description | |
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Parameter Settings: General | |||
How will you be using the dual port RAM? |
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Specifies how you use the dual port RAM. | |
How do you want to specify the memory size? |
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Determines whether to specify the memory size in words or bits. | |
Parameter Settings: Widths/ Blk Type | |||
How many <X>-bit words of memory? | — | Specifies the number of <X>-bit words. | |
Use different data widths on different ports | On/Off | Specifies whether to use different data widths on different ports. | |
When you select With one read port and one write port, the following options are available:
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— | Specifies the width of the input and output ports. | |
When you select With two read/write ports, the following options are available:
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What should the memory block type be? | Auto, M-RAM, M4K, M512, M9K, M10K, M144K, MLAB, M20K, LCs | Specifies the memory block type. The types of memory block that are available for selection depends on your target device. | |
How should the memory be implemented? |
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Specifies the logic cell implementation options. This option is enabled only when you choose LCs memory type. | |
Set the maximum block depth to | Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096 | Specifies the maximum block depth in words. This option is enabled only when you set the memory block type to Auto. | |
Parameter Settings: Clks/Rd, Byte En | |||
What clocking method would you like to use? | When you select With one read port and one write port, the following values are available:
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Specifies the clocking method to use.
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When you select With one read port and one write port, the following option is available: Create a ‘rden’ read enable signal |
— | Specifies whether to create a read enable signal for port B. | |
When you select With two read/write ports, the following option is available: Create a ‘rden_a’ and ‘rden_b’ read enable signal |
Specifies whether to create a read enable signal for port A and B. | ||
Create byte enable for port A | — | Specifies whether to create a byte enable for port A and B. Turn on these options if you want to mask the input data so that only specific bytes, nibbles, or bits of data are written. To enable byte enable for port A and port B, the data width ratio has to be 1 or 2 for the RAM: 1-PORT and RAM: 2-PORT IP cores. The option to create a byte enable for port B is only available when you select the With two read/write ports option. |
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Create byte enable for port B | — | ||
Enable error checking and correcting (ECC) to check and correct single bit errors and detect double errors | On/Off | Specifies whether to enable the ECC feature that corrects single bit errors and detects double errors at the output of the memory. This option is only available in devices that support M144K memory block type. | |
Enable error checking and correcting (ECC) to check and correct single bit errors, double adjacent bit errors, and detect triple adjacent bit errors | On/Off | Specifies whether to enable the ECC feature that corrects single bit errors, double adjacent bit errors, and detects triple adjacent bit errors at the output of the memory. This option is only available in devices that support M20K memory block type. | |
Parameter Settings: Regs/Clkens/Aclrs | |||
Which ports should be registered? When you select With one read port and one write port, the following options are available:
When you select With two read/write ports, the following options are available:
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On/Off | Specifies whether to register the read or write input and output ports. | |
More Options | When you select With one read port and one write port, the following options are available:
When you select With two read /write ports, the following options are available:
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On/Off | The read and write input ports are turned on by default. You only need to specify whether to register the Q output ports. |
Create one clock enable signal for each clock signal. | On/Off | Specifies whether to turn on the option to create one clock enable signal for each clock signal. | |
More Options | When you select With one read port and one write port, the following option is available:
When you select With two read /write ports, the following options are available:
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On/Off | Clock enable for port B input and output registers are turned on by default. You only need to specify whether to use clock enable for port A input and output registers. |
More Options | When you select With one read port and one write port, the following options are available:
When you select With two read /write ports, the following options are available:
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On/Off | Specifies whether to create clock enables for address registers. You can create these ports to act as an extra active low clock enable input for the address registers. |
Create an ‘aclr’ asynchronous clear for the registered ports. | On/Off | Specifies whether to create an asynchronous clear port for the registered ports. | |
More Options | When you select With one read port and one write port, the following options are available:
When you select With two read /write ports, the following options are available:
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On/Off | Specifies whether the ‘raddress’, ‘q_a’, and ‘q_b’ ports are cleared by the aclr port. |
Parameter Settings: Output 1 | |||
When you select With one read port and one write port, the following option is available:
When you select With two read /write ports, the following option is available:
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Specifies the output behavior when read-during-write occurs.
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Do not analyze the timing between write and read operation. Metastability issues are prevented by never writing and reading at the same address at the same time. | On/Off | Turn on this option when you want the RAM to output ‘don’t care’ or unknown values for read-during-write operation without analyzing the timing path. This option is only available for LUTRAM and is enabled when you set memory block type to MLAB. | |
Parameter Settings: Output 2 (This tab is only available when you select two read/ write ports) | |||
What should the ‘q_a’ output be when reading from a memory location being written to? |
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Specifies the output behavior when read-during-write occurs.
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What should the ‘q_b’ output be when reading from a memory location being written to? | |||
Get x’s for write masked bytes instead of old data when byte enable is used | On/Off | Turn on this option to obtain ‘X’ on the masked byte. | |
Parameter Settings: Mem Init | |||
Do you want to specify the initial content of the memory? |
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Specifies the initial content of the memory. To initialize the memory to zero, select No, leave it blank. To use a memory initialization file (.mif) or a hexadecimal (Intel-format) file (.hex), select Yes, use this file for the memory content data. |
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Enable Partial Reconfiguration Initialization Mode | On/Off | Initializes a clock enable circuit in the same PR region as the RAM. | |
Implement clock-enable circuitry for use in a partial reconfiguration region | On/Off | Specifies whether to implement clock-enable circuitry for use in a partial reconfiguration region. |