Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

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ID 683240
Date 9/17/2021
Public
Document Table of Contents
Document Table of Contents x
1. About Embedded Memory IP Cores 2. Embedded Memory IP Cores Getting Started 3. Functional Description 4. Embedded Memory Design Consideration 5. Parameters and Signals 6. Design Example 7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
1. About Embedded Memory IP Cores x
1.1. Features
2. Embedded Memory IP Cores Getting Started x
2.1. Changing Parameter Settings Manually 2.2. RAM and ROM Parameter Settings
3. Functional Description x
3.1. Memory Block Types 3.2. Write and Read Operations Triggering 3.3. Port Width Configurations 3.4. Mixed-width Port Configuration 3.5. Mixed-width Ratio Configuration 3.6. Maximum Block Depth Configuration 3.7. Clocking Modes and Clock Enable 3.8. Memory Blocks Address Clock Enable Support 3.9. Byte Enable 3.10. Asynchronous Clear 3.11. Read Enable 3.12. Read-During-Write 3.13. Power-Up Conditions and Memory Initialization 3.14. Error Correction Code 3.15. Freeze Logic
3.12. Read-During-Write x
3.12.1. Selecting RDW Output Choices for Various Memory Blocks
4. Embedded Memory Design Consideration x
4.1. Avoid Providing Non-Deterministic Input
5. Parameters and Signals x
5.1. RAM: 1-Port IP Core Parameters 5.2. RAM: 2-Port IP Core Parameters 5.3. ROM: 1-PORT IP Core Parameters 5.4. ROM: 2-PORT IP Core Parameters 5.5. Signals
6. Design Example x
6.1. External ECC Implementation with True-Dual-Port RAM
6.1. External ECC Implementation with True-Dual-Port RAM x
6.1.1. Generating the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-PORT IP Core 6.1.2. Simulating the Design
6.1.2. Simulating the Design x
6.1.2.1. Simulation Results
1. About Embedded Memory IP Cores
2. Embedded Memory IP Cores Getting Started
3. Functional Description
4. Embedded Memory Design Consideration
5. Parameters and Signals
6. Design Example
7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

5.1. RAM: 1-Port IP Core Parameters

Table 16.  RAM: 1-Port IP Core Parameters Description
Parameter Legal Values Description
Parameter Settings: Widths/Blk Type/Clks  
How wide should the ‘q’ output bus be? — Specifies the width of the ‘q’ output bus.
How many <X>-bit words of memory? — Specifies the number of <X>-bit words.
What should the memory block type be? Auto, M-RAM, M4K, M512, M9K, M10K, M144K, MLAB, M20K, LCs Specifies the memory block type. The types of memory block that are available for selection depends on your target device.
Set the maximum block depth to Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192,16384, 32768, 65536 Specifies the maximum block depth in words.
What clocking method would you like to use?
  • Single clock
  • Dual clock: use separate ‘input’ and ‘output’ clocks
 Specifies the clocking method to use.
  • Single clock—A single clock and a clock enable controls all registers of the memory block.
  • Dual clock: use separate ‘input’ and ‘output’ clocks—An input clock controls all registers related to the data input to the embedded memory block including data, address, byte enables, read enables, and write enables. An output clock controls the data output registers.
Parameter Settings: Regs/Clken/Byte Enable/Aclrs
Which ports should be registered?

The following options are available:

  • ‘data’ and ‘wren’ input ports
  • ‘address’ input port
  • ‘q’ output port
 On/Off Specifies whether to register the input and output ports.
Create one clock enable signal for each clock signal. Note: All registered ports are controlled by the enable signal(s) On/Off Specifies whether to turn on the option to create one clock enable signal for each clock signal.
More Options Use clock enable for port A input registers On/Off Specifies whether to use clock enable for port A input registers.
Use clock enable for port A output registers On/Off Specifies whether to use clock enable for port A output registers.
Create an ‘addressstall_a’ input port. On/Off Specifies whether to create a addressstall_a input port. You can create this port to act as an extra active low clock enable input for the address registers.
Create byte enable for port A On/Off Specifies whether to create a byte enable for port A. Turn on this option if you want to mask the input data so that only specific bytes, nibbles, or bits of data are written.

To enable byte enable for port A and port B, the data width ratio has to be 1 or 2 for the RAM: 1-PORT and RAM: 2-PORT IP cores.

What is the width of a byte for byte enables?
  • MLAB: 5 or 10
  • Other memory block types: 8 or 9
  • M10K and M20K: 8, 9, or 10
 Specifies the byte width of the byte enable port. The width of the data input port must be divisible by the byte size.
Create an ‘aclr’ asynchronous clear for the registered ports. On/Off Specifies whether to create an asynchronous clear port for the registered data, wren, address, q, and byteena_a ports.
More Options ‘q’ port On/Off Turn on this option for the ‘q’ port to be affected by the asynchronous clear signal. The disabled ports are not affected by the asynchronous clear signal.
Create a ‘rden’ read enable signal On/Off Specifies whether to create a read enable signal.
Parameter Settings: Read During Write Option
What should the q output be when reading from a memory location being written to? New data, Don’t Care Specifies the output behavior when read-during-write occurs.

New Data—New data is available on the rising edge of the same clock cycle on which it was written.

Don’t Care—The RAM outputs “don't care” or “unknown” values for read-during-write operation.

Get x’s for write masked bytes instead of old data when byte enable is used On/Off Turn on this option to obtain ‘X’ on the masked byte.

For M10K and M20K memory block, this option is not available if you specify New Data as the output behavior when RDW occurs.

Parameter Settings: Mem Init
Do you want to specify the initial content of the memory?
  • No, leave it blank
  • Yes, use this file for the memory content data
 Specifies the initial content of the memory.

To initialize the memory to zero, select No, leave it blank.

To use a memory initialization file (.mif) or a hexadecimal (Intel-format) file (.hex), select Yes, use this file for the memory content data.

Enable Partial Reconfiguration Initialization Mode On/Off Initializes a clock enable circuit in the same PR region as the RAM.
Allow In-System Memory Content Editor to capture and update content independently of the system clock On/Off Specifies whether to allow In-System Memory Content Editor to capture and update content independently of the system clock.
The ‘Instance ID’ of this RAM is None Specifies the RAM ID.
Implement clock-enable circuitry for use in a partial reconfiguration region On/Off Specifies whether to implement clock-enable circuitry for use in a partial reconfiguration region.
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