1.2. O-RAN Intel® FPGA IP Device Family Support
Intel offers the following device support levels for Intel FPGA IP:
- Advance support—the IP is available for simulation and compilation for this device family. FPGA programming file (.pof) support is not available for Quartus Prime Pro Stratix 10 Edition Beta software and as such IP timing closure cannot be guaranteed. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
- Preliminary support—Intel verifies the IP core with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. You can use it in production designs with caution.
- Final support—Intel verifies the IP with final timing models for this device family. The IP meets all functional and timing requirements for the device family. You can use it in production designs.
| Device Family | Support |
|---|---|
| Agilex™ 5 1 | Preliminary |
| Agilex™ 7 (E-tile) | Preliminary |
| Agilex™ 7 (F-tile) | Advance |
| Agilex™ 9 (F-tile) | Advance |
| Arria® 10 | Final |
| Stratix® 10 (H-, and E-tile devices only) | Final |
| Other device families | No support |
| Device Family | FPGA Fabric Speed Grade |
|---|---|
| Agilex™ 5 | 1 |
| Agilex™ 7 | 3 |
| Agilex™ 9 | 3 |
| Intel Arria 10 | 2 |
| Intel Stratix 10 | 2 |
1 The O-RAN IP design example does not support Agilex™ 5 devices.