O-RAN Intel® FPGA IP User Guide

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ID 683238
Date 1/24/2023
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Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP 2. Getting Started with the O-RAN Intel® FPGA IP 3. O-RAN IP Functional Description 4. O-RAN IP Registers 5. O-RAN Intel FPGA IP User Guide Archive 6. Document Revision History for the O-RAN Intel® FPGA IP User Guide
1. About the O-RAN Intel® FPGA IP x
1.1. O-RAN Intel® FPGA IP Features 1.2. O-RAN Intel® FPGA IP Device Family Support 1.3. Release Information for the O-RAN Intel® FPGA IP 1.4. O-RAN Intel® FPGA IP Performance and Resource Utilization
2. Getting Started with the O-RAN Intel® FPGA IP x
2.1. Obtaining, Installing, and Licensing the O-RAN IP 2.2. Parameterizing the O-RAN IP 2.3. Generated IP File Structure
2.2. Parameterizing the O-RAN IP x
2.2.1. O-RAN IP Parameters
3. O-RAN IP Functional Description x
3.1. O-RAN IP Signals 3.2. O-RAN Intel® FPGA IP Error Handling 3.3. O-RAN Reset Transactions 3.4. O-RAN IP Streaming Mode 3.5. O-RAN IP Performance Counters 3.6. O-RAN IP Transmission and Reception Window Threshold
1. About the O-RAN Intel® FPGA IP
2. Getting Started with the O-RAN Intel® FPGA IP
3. O-RAN IP Functional Description
4. O-RAN IP Registers
5. O-RAN Intel FPGA IP User Guide Archive
6. Document Revision History for the O-RAN Intel® FPGA IP User Guide

1. About the O-RAN Intel® FPGA IP

Updated for:
Intel® Quartus® Prime Design Suite 21.4
IP Version 1.6.0
The Extensible Radio Access Network (O-RAN WG4 Fronthaul Interface) defines a fronthaul interface between a lower-layer split distributed unit (DU) and remote unit (RU) in an Evolved Universal Terrestrial Access Network (E-UTRAN) and Next-Generation Radio Access Network (NG-RAN) system with a lower layer functional split-7-2x based architecture. The O-RAN IP implements control and user plane protocol specified in O-RAN-FH.CUS.0-v03.00. You can instantiate the O-RAN IP in both lower-layer split (LLS)-CU and RU modes. The IP does not support a synchronization plane. The IP splits protocol implementation between RTL targeting Intel® Arria® 10 and Intel® Stratix® 10 devices and software targeting an ARM processor.
Figure 1. Architecture of eNB and gNB

For more information about O-RAN, refer to the O-RAN Control and User Plane Specification and the O-RAN Management Plane Specification on the O-RAN website.

The O-RAN IP is compliant to O-RAN Fronthaul Control, User and Synchronization Plane Version 3.0 - April 2020 (O-RAN-WG4.CUS.0-v03.00)

The O-RAN IP supports category A RUs and precoding for LTE TM2-TM4 in category B RUs.

The IP supports the following data flows:

  • User-plane
    • Data Flow 1a: Flows of IQ Data in FFT frequency domain on downlink
    • Data Flow 1b: Flows of IQ Data in FFT frequency domain on uplink
    • Data Flow 1c: Flow of PRACH IQ data in FFT frequency domain
  • C-plane
    • Data Flow 2a-: Scheduling commands (downlink and uplink) and precoding commands
Figure 2. Lower layer fronthaul data flowsRepresents exclusion of Beamforming commands from data flow 2a in [1]

The O-RAN IP provides delay management service to ensure that it receives correct data over the fronthaul interface despite packet delay variation (PDV). The IP refers to concept and latency models from the eCPRI specification. The IP manages transmission and receiver windows, which you can place relative to the air interface based on predefined or measured transport delay. The IP exchanges RU parameters and network characteristic over M-plane messages. The IP monitors and counts packets transmitted or received out of the window to warn the other node and discard them if necessary. The IP also transmits and receives non-delay managed U-plane traffic for which normal windows are not applicable.

The IP interface enables integration with either eCPRI or IEEE 1914.3 radio over Ethernet (RoE) transport layer with 10Gbps and 25Gbps Ethernet link rates.

The IP supports static-bit-width of 8 to 16 bits fixed-point IQ format. The IP supports µ-law and block floating-point companding to reduce fronthaul interface bandwidth.

The IP supports 64 bits of data width for O-RAN mapper and demapper logics and 128 bits of data widths in the compression and decompression blocks.


Section Content
O-RAN Intel FPGA IP Features
O-RAN Intel FPGA IP Device Family Support
Release Information for the O-RAN Intel FPGA IP
O-RAN Intel FPGA IP Performance and Resource Utilization

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