O-RAN Intel® FPGA IP User Guide

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ID 683238
Date 1/24/2023
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Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP 2. Getting Started with the O-RAN Intel® FPGA IP 3. O-RAN IP Functional Description 4. O-RAN IP Registers 5. O-RAN Intel FPGA IP User Guide Archive 6. Document Revision History for the O-RAN Intel® FPGA IP User Guide
1. About the O-RAN Intel® FPGA IP x
1.1. O-RAN Intel® FPGA IP Features 1.2. O-RAN Intel® FPGA IP Device Family Support 1.3. Release Information for the O-RAN Intel® FPGA IP 1.4. O-RAN Intel® FPGA IP Performance and Resource Utilization
2. Getting Started with the O-RAN Intel® FPGA IP x
2.1. Obtaining, Installing, and Licensing the O-RAN IP 2.2. Parameterizing the O-RAN IP 2.3. Generated IP File Structure
2.2. Parameterizing the O-RAN IP x
2.2.1. O-RAN IP Parameters
3. O-RAN IP Functional Description x
3.1. O-RAN IP Signals 3.2. O-RAN Intel® FPGA IP Error Handling 3.3. O-RAN Reset Transactions 3.4. O-RAN IP Streaming Mode 3.5. O-RAN IP Performance Counters 3.6. O-RAN IP Transmission and Reception Window Threshold
1. About the O-RAN Intel® FPGA IP
2. Getting Started with the O-RAN Intel® FPGA IP
3. O-RAN IP Functional Description
4. O-RAN IP Registers
5. O-RAN Intel FPGA IP User Guide Archive
6. Document Revision History for the O-RAN Intel® FPGA IP User Guide

3.5. O-RAN IP Performance Counters

Table 19.  O-RAN IP Performance Counters
Counter Name Description
RX_TOTAL

The total number of control and user plane eCPRI messages type 0 and type 2 received. This counter is the sum of all valid and errored messages received.

RX_ON_TIME

The number of inbound user plane (eCPRI type 0) messages that arrive within the specified reception time window. The IP determines the timing window through t2a_max_up and t2a_min_up register setting. Some on time messages may have errors and are counted if they arrive within specified window time. The O-RAN IP doesn’t support transport fragmentation. If the received message is transport-fragmented, the counter increments according to the fragmented packets. The IP does not reassemble the full message before checking its arrival window.

RX_EARLY

The number of inbound user plane messages that the IP detects have arrived before the start of their designated receive window time. The IP determines the window start time through t2a_max_up register setting).

RX_LATE

The number of inbound user plane messages that the IP detect have arrived after the end of their designated receive window time. The IP determines the window start time through t2a_min_up register setting.

RX_ON_TIME_C

The number of valid inbound control plane (eCPRI type 2) messages that arrive within the specified time window. The IP determines the timing window through t2a_max_cp_dl and t2a_min_cp_dl register setting for downlink and t2a_max_cp_ul and t2a_min_cp_ul register settings for uplink.Some on time messages may have errors and are counted if they arrive within specified window time.

The IP implements this counter with an eAxC granularity with separate uplink and downlink counters.

  • eAxC DU_PortId (sink_rtc_id[15:12] and DataDirection = 1) = N, rx_on_time_c downlink counter N is incremented.
  • eAxC DU_PortId (sink_rtc_id[15:12] and DataDirection = 0) = N, rx_on_time_c uplink counter N is incremented.
RX_EARLY_C

The number of inbound control plane messages that the IP detects have arrived before the start of their designated receive window time. The IP determins the timing window start time through t2a_max_cp_dl register setting for downlink and t2a_max_cp_ul register setting for uplink. Some on time messages may have errors and are counted if they arrive within specified window time.

The IP implements this counter with an eAxC granularity with separate uplink and downlink counters.

  • eAxC DU_PortId (sink_rtc_id[15:12] and DataDirection = 1) = N, rx_early_c downlink counter N is incremented.
  • eAxC DU_PortId (sink_rtc_id[15:12] and DataDirection = 0) = N, rx_early_c uplink counter N is incremented.
RX_LATE_C

The number of inbound control plane messages that the IP detects to arrive after the end of their designated receive window time. The IP determines timing window start time through t2a_min_cp_dl register setting for downlink and t2a_min_cp_ul register setting for uplink. Some on time messages may have errors and are counted if they arrive within the specified window time.

The IP implements this counter with an eAxC granularity with separate uplink and downlink counters.

  • eAxC DU_PortId (sink_rtc_id[15:12] and DataDirection = 1) = N, rx_late_c downlink counter N is incremented.
  • eAxC DU_PortId (sink_rtc_id[15:12] and DataDirection = 0) = N, rx_late_c uplink counter N is incremented.
TX_TOTAL The number of valid outbound control and user plane messages (type 0 and type 2).
TX_TOTAL_C The number of valid outbound control plane messages (type 2).

The IP implements the performance counters in the performance indicator logic block. All the performance counters are 64 bits wide. All counters above are wrap-around counters and it automatically go from their maximum and final value to zero and continue to operate. These counters are reset to 0 when you assert csr_rst_n or set the performance counter reset bit in the functional_mode register. These counters are counted using clk_tx for outbound counters (TX_*) and clk_rx for inbound counters (RX_*).

DU_PortId for uplink and downlink control plane packets can be derived from sink_rtc_id[15:12] signal through the transport interface.

Level Two Title