Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 4/01/2024
Public

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1.5. Precompiled Component (PCC) Generation Flow

Precompiled Components (PCC) generation flow is a compilation stage that runs between IP Generation and Analysis & Synthesis stages on the compilation dashboard. It synthesizes and caches the results of the Intel® FPGA IP components in your design.

PCC generation reduces Synthesis compile time through the following steps and allows you to iterate and go to post-synthesis timing analysis stages faster and reduce the development cycle time:

  1. Synthesizes Intel® FPGA IP components in your design.
  2. Generates and caches IP compilation results in your project's ocs_cache_dir (IP cache) directory.
  3. Reuses the IP cache in subsequent Synthesis runs.
Figure 6. PCC Generation

By default, the PCC generation flow is disabled. You can enable it from Assignments > Settings > Board and IP Settings dialog as shown in the following:

If the PCC generation flow compiles successfully, you can view the Precompiled Components compilation report for each IP that participates in the flow under the Compilation Reports dialog.

Advantages of PCC Generation Flow

  • Each unique IP is generated only once and cached, so the subsequent Synthesis run does not perform PCC generation if you have not modified any IP in your design.
  • If you modify any IP, the PCC generation flow synthesizes only that IP and skips synthesizing the remaining IPs.
  • The PCC generation process occurs in parallel for each IP.
  • Synthesis compile time savings scales with the proportion of the design that is IP.