Visible to Intel only — GUID: syu1484866705904
Ixiasoft
2.1. Compilation Overview
2.2. Using the Compilation Dashboard
2.3. Design Netlist Infrastructure (DNI)
2.4. Design Synthesis
2.5. Design Place and Route
2.6. Incremental Optimization Flow
2.7. Fast Forward Compilation Flow
2.8. Full Compilation Flow
2.9. Exporting Compilation Results
2.10. Integrating Other EDA Tools
2.11. Synthesis Language Support
2.12. Compiler Optimization Techniques
2.13. Synthesis Settings Reference
2.14. Fitter Settings Reference
2.15. Design Compilation Revision History
2.9.1. Exporting a Version-Compatible Compilation Database
2.9.2. Importing a Version-Compatible Compilation Database
2.9.3. Creating a Design Partition
2.9.4. Exporting a Design Partition
2.9.5. Reusing a Design Partition
2.9.6. Viewing Quartus Database File Information
2.9.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results
3.2. Strategies to Reduce the Overall Compilation Time
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
3.4. Reducing Placement Time
3.5. Reducing Routing Time
3.6. Reducing Static Timing Analysis Time
3.7. Setting Process Priority
3.8. Reducing Compilation Time Revision History
Visible to Intel only — GUID: syu1484866705904
Ixiasoft
2.7.3.2. HyperFlex Settings
The HyperFlex settings page controls whether Fast Forward Compilation analyzes and reports results for specific logical structures in the Intel® Hyperflex™ architecture. You access this page by clicking Assignments > Settings > HyperFlex. Turn on Run Fast Forward Timing Closure Recommendations during compilation to enable Fast Forward analysis during the compilation flow by default. To access the following additional settings, click Advanced Settings.
Option | Description |
---|---|
Fast Forward Compile Asynchronous Clears | Specifies how Fast Forward analysis accounts for registers with asynchronous clear signals. The options are:
|
Fast Forward Compile Cut All Clock Transfers | Cuts all clock transfers in Fast Forward Compilation analysis. |
Fast Forward Compile Fully Registered DSP Blocks | Specifies how Fast Forward analysis accounts for DSP blocks that limit performance. Enable this option to generate results as if all DSP blocks are fully registered. |
Fast Forward Compile Fully Registered RAM Blocks | Specifies how Fast Forward analysis accounts for RAM blocks that limit performance. Enable this option to analyze the blocks as fully registered. |
Fast Forward Compile Maximum Additional Pipeline Stages | Specifies the maximum number of pipeline stages that Fast Forward compilation explores. |
Fast Forward Compile User Preserve Directives | Specifies how Fast Forward compilation accounts for restrictions from user-preserve directives. |