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2.1. Compilation Overview
2.2. Using the Compilation Dashboard
2.3. Design Synthesis
2.4. Design Place and Route
2.5. Incremental Optimization Flow
2.6. Fast Forward Compilation Flow
2.7. Full Compilation Flow
2.8. Exporting Compilation Results
2.9. Integrating Other EDA Tools
2.10. Synthesis Language Support
2.11. Compiler Optimization Techniques
2.12. Synthesis Settings Reference
2.13. Fitter Settings Reference
2.14. Design Compilation Revision History
2.8.1. Exporting a Version-Compatible Compilation Database
2.8.2. Importing a Version-Compatible Compilation Database
2.8.3. Creating a Design Partition
2.8.4. Exporting a Design Partition
2.8.5. Reusing a Design Partition
2.8.6. Viewing Quartus Database File Information
2.8.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results
3.2. Strategies to Reduce the Overall Compilation Time
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
3.4. Reducing Placement Time
3.5. Reducing Routing Time
3.6. Reducing Static Timing Analysis Time
3.7. Setting Process Priority
3.8. Reducing Compilation Time Revision History
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2.5.2.1.4. Validating Timing Constraints with Snapshot Viewer
- To run the Plan or Place stage of the Fitter, double-click the stage in the Compilation Dashboard.
- After the stage completes, click the Snapshot Viewer icon for that stage in the Compilation Dashboard. The Snapshot Viewer opens.
- Under Validate Constraints, double-click Timing Exceptions. The Timing Exception Results report opens, allowing additional analysis and locating to other tools.
Figure 27. Validate Constraints—Timing Exceptions Report
- Under Validate Constraints, double-click Check Unregistered Ports.
Figure 28. Validate Constraints—Check Unregistered Ports Report