Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

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ID 683236
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Design Compilation 3. Reducing Compilation Time 4. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Design Compilation x
2.1. Compilation Overview 2.2. Using the Compilation Dashboard 2.3. Design Synthesis 2.4. Design Place and Route 2.5. Incremental Optimization Flow 2.6. Fast Forward Compilation Flow 2.7. Full Compilation Flow 2.8. Exporting Compilation Results 2.9. Integrating Other EDA Tools 2.10. Synthesis Language Support 2.11. Compiler Optimization Techniques 2.12. Synthesis Settings Reference 2.13. Fitter Settings Reference 2.14. Design Compilation Revision History
2.1. Compilation Overview x
2.1.1. Compilation Flows 2.1.2. Compilation Hierarchy 2.1.3. Compilation Monitoring
2.3. Design Synthesis x
2.3.1. Running Synthesis 2.3.2. Viewing Synthesis Reports
2.3.1. Running Synthesis x
2.3.1.1. Preserving Registers During Synthesis 2.3.1.2. Preserving Signals for Monitoring and Debugging
2.4. Design Place and Route x
2.4.1. Running the Fitter 2.4.2. Viewing Fitter Reports
2.4.1. Running the Fitter x
2.4.1.1. Fitter Commands 2.4.1.2. Disabling or Enabling Physical Synthesis Optimization
2.4.2. Viewing Fitter Reports x
2.4.2.1. Plan Stage Reports 2.4.2.2. Place Stage Reports 2.4.2.3. Route Stage Reports 2.4.2.4. Retime Stage Reports 2.4.2.5. Finalize Stage Reports
2.4.2.2. Place Stage Reports x
2.4.2.2.1. Global Signal Visualization Report
2.4.2.3. Route Stage Reports x
2.4.2.3.1. Global Router Congestion Hotspot Summary Report 2.4.2.3.2. Global Router Wire Utilization Map Report
2.5. Incremental Optimization Flow x
2.5.1. Concurrent Analysis During Synthesis or Fitting 2.5.2. Analyzing Compiler Snapshots 2.5.3. Validating Periphery (I/O) after the Plan Stage
2.5.2. Analyzing Compiler Snapshots x
2.5.2.1. Running Snapshot Viewer
2.5.2.1. Running Snapshot Viewer x
2.5.2.1.1. Analyzing Failing Paths with Snapshot Viewer 2.5.2.1.2. Analyzing Clocking with Snapshot Viewer 2.5.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 2.5.2.1.4. Validating Timing Constraints with Snapshot Viewer 2.5.2.1.5. Analyzing Congestion with Snapshot Viewer
2.6. Fast Forward Compilation Flow x
2.6.1. Step 1: Run Register Retiming 2.6.2. Step 2: Review Retiming Results 2.6.3. Step 3: Run Fast Forward Compile 2.6.4. Step 4: Review Fast Forward Results 2.6.5. Step 5: Implement Fast Forward Recommendations 2.6.6. Retiming Restrictions and Workarounds
2.6.2. Step 2: Review Retiming Results x
2.6.2.1. Locate Critical Chains
2.6.3. Step 3: Run Fast Forward Compile x
2.6.3.1. Fast Forward Compile By Hierarchy 2.6.3.2. HyperFlex Settings
2.6.4. Step 4: Review Fast Forward Results x
2.6.4.1. Clock Fmax Summary Report 2.6.4.2. Fast Forward Details Report
2.7. Full Compilation Flow x
2.7.1. Full Compilation Flow with Temporary Optimization Mode
2.8. Exporting Compilation Results x
2.8.1. Exporting a Version-Compatible Compilation Database 2.8.2. Importing a Version-Compatible Compilation Database 2.8.3. Creating a Design Partition 2.8.4. Exporting a Design Partition 2.8.5. Reusing a Design Partition 2.8.6. Viewing Quartus Database File Information 2.8.7. Clearing Compilation Results
2.8.6. Viewing Quartus Database File Information x
2.8.6.1. QDB File Attribute Types
2.9. Integrating Other EDA Tools x
2.9.1. Generating a VQM Netlist for other EDA Tools
2.10. Synthesis Language Support x
2.10.1. Verilog and SystemVerilog Synthesis Support 2.10.2. VHDL Synthesis Support
2.10.1. Verilog and SystemVerilog Synthesis Support x
2.10.1.1. Verilog HDL Input Settings (Settings Dialog Box) 2.10.1.2. Design Libraries 2.10.1.3. Verilog HDL Configuration 2.10.1.4. Initial Constructs and Memory System Tasks 2.10.1.5. Verilog HDL Macros
2.10.1.3. Verilog HDL Configuration x
2.10.1.3.1. Hierarchical Design Configurations Gate-level code for the 0 (zero) bit of the adder Use configuration cfg1 for first instance of eight-bit adder
2.10.2. VHDL Synthesis Support x
2.10.2.1. VHDL Input Settings (Settings Dialog Box) 2.10.2.2. VHDL Standard Libraries and Packages 2.10.2.3. VHDL wait Constructs 2.10.2.4. VHDL-2019 Conditional Analysis Tool Directives
2.11. Compiler Optimization Techniques x
2.11.1. Compiler Optimization Modes 2.11.2. Allow Register Retiming 2.11.3. Automatic Gated Clock Conversion 2.11.4. Enable Intermediate Fitter Snapshots 2.11.5. Fast Preserve Option 2.11.6. Fractal Synthesis Optimization
2.11.6. Fractal Synthesis Optimization x
2.11.6.1. Enabling or Disabling Fractal Synthesis
2.12. Synthesis Settings Reference x
2.12.1. Advanced Synthesis Settings
3. Reducing Compilation Time x
3.1. Factors Affecting Compilation Results 3.2. Strategies to Reduce the Overall Compilation Time 3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 3.4. Reducing Placement Time 3.5. Reducing Routing Time 3.6. Reducing Static Timing Analysis Time 3.7. Setting Process Priority 3.8. Reducing Compilation Time Revision History
3.2. Strategies to Reduce the Overall Compilation Time x
3.2.1. Running the ECO Compilation Flow 3.2.2. Enabling Multi-Processor Compilation 3.2.3. Using Block-Based Compilation
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time x
3.3.1. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 3.3.2. Use Appropriate Coding Style to Reduce Synthesis Time
3.4. Reducing Placement Time x
3.4.1. Placement Effort Multiplier Settings
3.5. Reducing Routing Time x
3.5.1. Identifying Routing Congestion with the Chip Planner
3.5.1. Identifying Routing Congestion with the Chip Planner x
3.5.1.1. Areas with Routing Congestion 3.5.1.2. Congestion due to HDL Coding style
1. Answers to Top FAQs
2. Design Compilation
3. Reducing Compilation Time
4. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Intel® Quartus® Prime Pro Edition User Guides

2.10.1.3.1. Hierarchical Design Configurations

A design can have more than one configuration. For example, you can define a configuration that specifies the source code you use in particular instances in a sub-hierarchy, and then define a configuration for a higher level of the design.

For example, suppose a subhierarchy of a design is an eight-bit adder, and the RTL Verilog code describes the adder in a logical library named rtllib. The gate-level code describes the adder in the gatelib logical library. If you want to use the gate-level code for the 0 (zero) bit of the adder and the RTL level code for the other seven bits, the configuration might appear as follows:

Gate-level code for the 0 (zero) bit of the adder

config cfg1;
design aLib.eight_adder;
default liblist rtllib;
instance adder.fulladd0 liblist gatelib;
endconfig

If you are instantiating this eight-bit adder eight times to create a 64-bit adder, use configuration cfg1 for the first instance of the eight-bit adder, but not in any other instance. A configuration that performs this function is shown below:

Use configuration cfg1 for first instance of eight-bit adder 

config cfg2;
design bLib.64_adder;
default liblist bLib;
instance top.64add0 use work.cfg1:config;
endconfig
Note: The name of the unbound module may be different from the name of the cell that is bounded to the instance.
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