Visible to Intel only — GUID: mtr1423531881372
Ixiasoft
2.1. Compilation Overview
2.2. Using the Compilation Dashboard
2.3. Design Synthesis
2.4. Design Place and Route
2.5. Incremental Optimization Flow
2.6. Fast Forward Compilation Flow
2.7. Full Compilation Flow
2.8. Exporting Compilation Results
2.9. Integrating Other EDA Tools
2.10. Synthesis Language Support
2.11. Compiler Optimization Techniques
2.12. Synthesis Settings Reference
2.13. Fitter Settings Reference
2.14. Design Compilation Revision History
2.8.1. Exporting a Version-Compatible Compilation Database
2.8.2. Importing a Version-Compatible Compilation Database
2.8.3. Creating a Design Partition
2.8.4. Exporting a Design Partition
2.8.5. Reusing a Design Partition
2.8.6. Viewing Quartus Database File Information
2.8.7. Clearing Compilation Results
3.1. Factors Affecting Compilation Results
3.2. Strategies to Reduce the Overall Compilation Time
3.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
3.4. Reducing Placement Time
3.5. Reducing Routing Time
3.6. Reducing Static Timing Analysis Time
3.7. Setting Process Priority
3.8. Reducing Compilation Time Revision History
Visible to Intel only — GUID: mtr1423531881372
Ixiasoft
2.6.3. Step 3: Run Fast Forward Compile
Fast Forward compilation generates design-specific timing closure recommendations, and predicts the maximum performance after the removal of all timing restrictions.
You can review the Fast Forward recommendations and implement the changes in your RTL that remove timing restrictions and enable mobility within the netlist for register Hyper-Retiming.
You can run Fast Forward compilation for the entire design hierarchy, or for only specific instances in the hierarchy, as Fast Forward Compile By Hierarchy describes.
To generate Fast Forward timing closure recommendations, follow these steps:
- Optionally, specify any of the following options if you want to automate or refine Fast Forward analysis:
- If you want to run Fast Forward compilation during each full compilation, click Assignments > Settings > Compiler Settings > HyperFlex and enable Run Fast Forward Timing Closure Recommendations during compilation.
- If you want to modify how Fast Forward compilation interprets specific I/O and block types, click Assignments > Settings > Compiler Settings > HyperFlex > Advanced Settings.
- On the Compilation Dashboard, click Fast Forward Timing Closure Recommendations. The Compiler runs prerequisite synthesis or Fitter stages automatically, as needed, and generates timing closure recommendations in the Compilation Report.
Figure 39. Running Fast Forward Compilation
- View timing closure recommendations in the Compilation Report to evaluate design performance and implement key RTL performance improvements, as Step 4: Review Fast Forward Results describes.