Stratix® 10 DX Device Overview

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ID 683225
Date 9/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 DX Device Overview
1. Intel® Stratix® 10 DX Device Overview x
1.1. Intel® Stratix® 10 DX Devices 1.2. Intel® Stratix® 10 DX Features Summary 1.3. Intel® Stratix® 10 DX Block Diagram 1.4. Intel® Stratix® 10 DX Family Plan 1.5. Intel® Hyperflex™ Core Architecture 1.6. Heterogeneous 3D SiP Transceiver Tiles 1.7. Intel® Stratix® 10 DX Transceivers 1.8. Heterogeneous 3D Stacked HBM2 DRAM Memory 1.9. External Memory and General Purpose I/O 1.10. Adaptive Logic Module (ALM) 1.11. Core Clocking 1.12. I/O PLLs 1.13. Internal Embedded Memory 1.14. Variable Precision DSP Block 1.15. Hard Processor System (HPS) 1.16. Power Management 1.17. Device Configuration and Secure Device Manager (SDM) 1.18. Device Security 1.19. Configuration via Protocol Using PCI Express* 1.20. Partial and Dynamic Reconfiguration 1.21. Fast Forward Compile 1.22. Single Event Upset (SEU) Error Detection and Correction 1.23. Document Revision History for the Intel® Stratix® 10 DX Device Overview
1.4. Intel® Stratix® 10 DX Family Plan x
1.4.1. Available Options
1.7. Intel® Stratix® 10 DX Transceivers x
1.7.1. Intel® P-Tile Transceivers and Hard IP 1.7.2. Intel® E-Tile Transceivers and Hard IP
1.15. Hard Processor System (HPS) x
1.15.1. Key Features of the Intel® Stratix® 10 HPS
1. Intel® Stratix® 10 DX Device Overview

1.9. External Memory and General Purpose I/O

In addition to the bandwidth delivered by the in-package HBM2 DRAM near memory (in selected devices), all Intel® Stratix® 10 DX devices offer substantial external memory bandwidth, supporting DDR4 memory interfaces running at up to 2666 Mbps and DDR-T memory interfaces at up to 2400 megatransfers per second.

This bandwidth is provided along with the ease of design, lower power, and resource efficiencies of hardened high-performance memory controllers. The external memory interfaces can be configured up to a maximum width of 144 bits when using either hard or soft memory controllers.

Figure 9. Hard Memory Controller

Each I/O bank contains 48 general purpose I/Os and a high-efficiency hard memory controller capable of supporting many different memory types, each with different performance capabilities. The hard memory controller is also capable of being bypassed and replaced by a soft controller implemented in user logic. The I/Os each have a hardened double data rate (DDR) read/write path (PHY) capable of performing key memory interface functionality such as:

  • Read/write leveling
  • FIFO buffering to lower latency and improve margin
  • Timing calibration
  • On-chip termination

The timing calibration is aided by the inclusion of hard microcontrollers based on Intel’s Nios® II technology, specifically tailored to control the calibration of multiple memory interfaces. This calibration allows the Intel® Stratix® 10 DX device to compensate for any changes in process, voltage, or temperature either within the device itself, or within the external memory device. The advanced calibration algorithms ensure maximum bandwidth and robust timing margin across all operating conditions. For the list of features available with the Intel® DDR-T memory controller IP, see External Memory Interface and the DDR-T Memory Controller IP User Guide. For access to the DDR-T Memory Controller IP User Guide, contact My Intel support.

Table 9.  External Memory Interface PerformanceThe listed speeds are for the 1-rank case.

Interface

Controller Type

Performance

(maximum rate possible)
Intel® DDR-T Soft

2400 megatransfers per second

(one module per controller)

DDR4

Hard

2666 Mbps

DDR3

Hard

2133 Mbps

QDRII+

Soft

1,100 Mtps

QDRII+ Xtreme

Soft

1,266 Mtps

QDRIV

Soft

2,133 Mtps

RLDRAM III

Soft

2400 Mbps

RLDRAM II

Soft

533 Mbps

Intel® Stratix® 10 DX devices also feature general purpose I/Os capable of supporting a wide range of single-ended and differential I/O interfaces. LVDS rates up to 1.6 Gbps are supported, with each pair of pins having both a differential driver and a differential input buffer. This enables configurable direction for each LVDS pair.

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