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1.1. Intel® Stratix® 10 DX Devices
1.2. Intel® Stratix® 10 DX Features Summary
1.3. Intel® Stratix® 10 DX Block Diagram
1.4. Intel® Stratix® 10 DX Family Plan
1.5. Intel® Hyperflex™ Core Architecture
1.6. Heterogeneous 3D SiP Transceiver Tiles
1.7. Intel® Stratix® 10 DX Transceivers
1.8. Heterogeneous 3D Stacked HBM2 DRAM Memory
1.9. External Memory and General Purpose I/O
1.10. Adaptive Logic Module (ALM)
1.11. Core Clocking
1.12. I/O PLLs
1.13. Internal Embedded Memory
1.14. Variable Precision DSP Block
1.15. Hard Processor System (HPS)
1.16. Power Management
1.17. Device Configuration and Secure Device Manager (SDM)
1.18. Device Security
1.19. Configuration via Protocol Using PCI Express*
1.20. Partial and Dynamic Reconfiguration
1.21. Fast Forward Compile
1.22. Single Event Upset (SEU) Error Detection and Correction
1.23. Document Revision History for the Intel® Stratix® 10 DX Device Overview
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1.11. Core Clocking
Core clocking in Intel® Stratix® 10 DX devices makes use of programmable clock tree synthesis.
This technique uses dedicated clock tree routing and switching circuits, and allows the Intel® Quartus® Prime software to create the exact clock trees required for your design. Clock tree synthesis minimizes clock tree insertion delay, reduces dynamic power dissipation in the clock tree and allows greater clocking flexibility in the core while still maintaining backwards compatibility with legacy global and regional clocking schemes.
The core clock network in Intel® Stratix® 10 DX devices supports the high-performance Intel® Hyperflex™ core architecture and also supports the hard memory controllers at rates up to 2666 Mbps with a quarter rate transfer to the core. The core clock network is driven by either dedicated clock input pins, or integer I/O PLLs.