Stratix® 10 DX Device Overview

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ID 683225
Date 9/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 DX Device Overview
1. Intel® Stratix® 10 DX Device Overview x
1.1. Intel® Stratix® 10 DX Devices 1.2. Intel® Stratix® 10 DX Features Summary 1.3. Intel® Stratix® 10 DX Block Diagram 1.4. Intel® Stratix® 10 DX Family Plan 1.5. Intel® Hyperflex™ Core Architecture 1.6. Heterogeneous 3D SiP Transceiver Tiles 1.7. Intel® Stratix® 10 DX Transceivers 1.8. Heterogeneous 3D Stacked HBM2 DRAM Memory 1.9. External Memory and General Purpose I/O 1.10. Adaptive Logic Module (ALM) 1.11. Core Clocking 1.12. I/O PLLs 1.13. Internal Embedded Memory 1.14. Variable Precision DSP Block 1.15. Hard Processor System (HPS) 1.16. Power Management 1.17. Device Configuration and Secure Device Manager (SDM) 1.18. Device Security 1.19. Configuration via Protocol Using PCI Express* 1.20. Partial and Dynamic Reconfiguration 1.21. Fast Forward Compile 1.22. Single Event Upset (SEU) Error Detection and Correction 1.23. Document Revision History for the Intel® Stratix® 10 DX Device Overview
1.4. Intel® Stratix® 10 DX Family Plan x
1.4.1. Available Options
1.7. Intel® Stratix® 10 DX Transceivers x
1.7.1. Intel® P-Tile Transceivers and Hard IP 1.7.2. Intel® E-Tile Transceivers and Hard IP
1.15. Hard Processor System (HPS) x
1.15.1. Key Features of the Intel® Stratix® 10 HPS
1. Intel® Stratix® 10 DX Device Overview

1.2. Intel® Stratix® 10 DX Features Summary

Table 1.   Intel® Stratix® 10 DX Device Features

Feature

Description

Configuration
  • Dedicated Secure Device Manager
  • Software programmable device configuration
  • Serial and parallel flash interface
  • Configuration via protocol (CvP) using PCI Express* Gen1/Gen2/Gen3/Gen4
  • Fine-grained partial reconfiguration of core fabric
  • Dynamic reconfiguration of transceivers and PLLs
  • Comprehensive set of security features including AES-256, SHA-256/384, and ECDSA-256/384 accelerators, and multi-factor authentication
  • Physically Unclonable Function (PUF) service

Core clock networks
  • Programmable clock tree synthesis, backwards compatible with global, regional and peripheral clock networks
  • Clocks only synthesized where needed, to minimize dynamic power
  • 667 MHz external memory interface clocking, supports 2666 Mbps DDR4 interface
  • 800 MHz LVDS interface clocking, supports 1600 Mbps LVDS interface

Core process technology
  • 14 nm Intel® tri-gate (FinFET) process technology
  • SmartVID controlled core voltage, standard power devices

Embedded hard IP
  • PCIe* Gen1/Gen2/Gen3/Gen4 x16 complete protocol stack, endpoint and root port, multiple independent controllers, SR-IOV, VIRTIO, Intel® Scalable IOV, and transaction layer bypass
  • Intel® UPI hard IP requires Intel® soft IP (separate licensing required, selected customers only, 1SD210 and 1SD280 devices only)
  • 100 GbE MAC, Reed-Solomon FEC hard IP, and KP-FEC hard IP
  • DDR4/DDR3 hard memory controller (RLDRAM3/QDR II+/QDR IV using soft memory controller)
  • HBM2 DRAM hard memory controller (select devices)
  • Hard Processor system, Quad-core 64-bit Arm* Cortex* -A53 (select devices)

General purpose I/Os
  • Up to 816 total GPIO available
  • 1.6 Gbps LVDS—every pair can be configured as an input or output
  • Up to 2400 megatransfers per second DDR-T external memory interface ( Intel® soft IP license required)
  • 1333 MHz/2666 Mbps DDR4 external memory interface
  • 1067 MHz/2133 Mbps DDR3 external memory interface
  • 1.2 V to 1.8 V single-ended LVCMOS/LVTTL interfacing
  • On-chip termination (OCT)

High performance monolithic core fabric
  • Intel® Hyperflex™ core architecture with Hyper-Registers everywhere throughout the interconnect routing and at the inputs of all functional blocks
  • Monolithic fabric minimizes compile times and increases logic utilization
  • Enhanced adaptive logic module (ALM)
  • Improved multi-rack routing architecture reduces congestion and improves compile times
  • Hierarchical core clocking architecture with programmable clock tree synthesis
  • Fine-grained partial reconfiguration

Internal memory blocks
  • eSRAM—47.25 Mbit with hard ECC support (select devices)
  • M20K—20 kilobit (Kb) with hard ECC support
  • MLAB—640 bit distributed LUTRAM

Low power serial transceivers
  • Up to 84 total transceivers available
  • Continuous operating range of 1 Gbps to 57.8 Gbps PAM4 and 28.9 Gbps NRZ (E-tile transceivers)
  • Backplane support up to 57.8 Gbps PAM4 and 28.9 Gbps NRZ (E-tile transceivers)
  • Transmit pre-emphasis and de-emphasis
  • Dynamic partial reconfiguration of individual transceiver channels
  • On-chip instrumentation (Eye Viewer non-intrusive data eye monitoring)

Packaging
  • Intel® Embedded Multi-die Interconnect Bridge (EMIB) packaging technology
  • 1.0 mm ball-pitch FBGA packaging
  • Lead and lead-free package options

Phase locked loops (PLLs)
  • Integer PLLs adjacent to general purpose I/Os, support external memory, and LVDS interfaces, clock delay compensation, zero delay buffering

Power management
  • SmartVID controlled core voltage, standard power devices
  • Intel® Quartus® Prime Pro Edition integrated power analysis

Software and tools
  • Intel® Quartus® Prime Pro Edition design suite with new compiler and Hyper-Aware design flow
  • Fast Forward compiler to allow Intel® Hyperflex™ architecture performance exploration
  • Transceiver toolkit
  • Platform Designer system integration tool
  • DSP Builder system integration tool
  • OpenCL* support

Variable precision DSP blocks
  • IEEE 754-compliant hard single-precision floating point capability
  • Supports signal processing with precision ranging from 18x19 up to 54x54
  • Native 27x27 and 18x19 multiply modes
  • 64-bit accumulator and cascade for systolic FIRs
  • Internal coefficient memory banks
  • Pre-adder/subtractor improves efficiency
  • Additional pipeline register increases performance and reduces power
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