O-RAN Intel® FPGA IP Design Example User Guide

Download PDF
ID 683218
Date 2/20/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP Design Example 2. Getting Started with the O-RAN Intel® FPGA IP Design Example 3. O-RAN Intel® FPGA IP Design Example Functional Description 4. O-RAN IP Design Example User Guide Archives 5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide
2. Getting Started with the O-RAN Intel® FPGA IP Design Example x
2.1. Generating the O-RAN IP Design Example 2.2. Simulating the O-RAN IP Design Example 2.3. Operating the O-RAN IP Design Example
2.1. Generating the O-RAN IP Design Example x
2.1.1. O-RAN IP Design Example Parameters
2.2. Simulating the O-RAN IP Design Example x
2.2.1. Simulating the O-RAN Design Example for Intel Agilex F-Tile Devices 2.2.2. Enabling Dynamic Reconfiguation to the Ethernet IP 2.2.3. O-RAN IP Design Example Testbench
2.3. Operating the O-RAN IP Design Example x
2.3.1. Generating and Downloading the Programming .elf File
1. About the O-RAN Intel® FPGA IP Design Example
2. Getting Started with the O-RAN Intel® FPGA IP Design Example
3. O-RAN Intel® FPGA IP Design Example Functional Description
4. O-RAN IP Design Example User Guide Archives
5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide

2.1.1. O-RAN IP Design Example Parameters

Table 1.  O-RAN IP Design Example Parameters
Parameter Values Description
Generate Example Design for Simulation Select to generate the simulation files. For example for F-tile designs that support simulation only.
Synthesis Select to generate the synthesis files
Synthesis & Simulation Select to generate the synthesis and simulation files.
Generate File Format Verilog VHDL

Select either Verilog HDL or VHDL as the format for generated RTL files simulation and synthesis. Some submodules are generated in mixed (both Verilog HDL and VHDL) formats.

Select board Agilex SI Development Kit

Select to allow you to test the design example on the selected Intel development kit. The wizard automatically selects the target device to match the device on the selected Intel development kit. Select AGFB014R24A2E3V for an Intel Agilex 10 E-tile device. If your board revision has a different speed grade of these devices above, you can correct it.

Arria Signal Integrity Development Kit

Select to allow you to test the design example on the selected Intel development kit. The wizard automatically selects the target device to match the device on the selected Intel development kit. Select 10AX115S2F45I1SG for an Intel® Arria® 10 device. If your board revision has a different speed grade of these devices above, you can correct it.

Stratix 10 Signal Integrity Development Kit

Select to allow you to test the design example on the selected Intel development kit. The wizard automatically selects the target device to match the device on the selected Intel development kit. Select 1SX280HU2F50E2VG for Intel® Stratix® 10 H-Tile and 1ST280EY2F55E2VG for Intel® Stratix® 10 E-Tile. If your board revision has a different speed grade of these devices above, you can correct it.
No Development Kit

Select to exclude development kit hardware for the design example. For example for F-tile designs that support simulation only.

Number of channels 1 to 4 Select the number of channels to generate in the design example.
Level Two Title