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Ixiasoft
1. About the O-RAN Intel® FPGA IP Design Example
2. Getting Started with the O-RAN Intel® FPGA IP Design Example
3. O-RAN Intel® FPGA IP Design Example Functional Description
4. O-RAN IP Design Example User Guide Archives
5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide
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Ixiasoft
1. About the O-RAN Intel® FPGA IP Design Example
Updated for: |
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Intel® Quartus® Prime Design Suite 22.1 |
IP Version 1.7.0 |
The design example allows you to simulate, compile, and test your O-RAN IP instance on various development boards. The design example includes Ethernet IP, eCPRI IP, eCPRI IOPLL, PTP IOPLL, and a test wrapper.
The compiled hardware design example runs on the:
- Intel® Agilex™ F-Series Transceiver-SoC Development Kit for the E-tile design examples
- Intel® Agilex™ I-Series Transceiver-SoC Development Kit
- Intel® Arria® 10 GX Signal Integrity Development Kit
- Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit for the H-tile design examples
- Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit for the E-tile design examples
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