O-RAN Intel® FPGA IP Design Example User Guide

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ID 683218
Date 2/20/2023
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Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP Design Example 2. Getting Started with the O-RAN Intel® FPGA IP Design Example 3. O-RAN Intel® FPGA IP Design Example Functional Description 4. O-RAN IP Design Example User Guide Archives 5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide
2. Getting Started with the O-RAN Intel® FPGA IP Design Example x
2.1. Generating the O-RAN IP Design Example 2.2. Simulating the O-RAN IP Design Example 2.3. Operating the O-RAN IP Design Example
2.1. Generating the O-RAN IP Design Example x
2.1.1. O-RAN IP Design Example Parameters
2.2. Simulating the O-RAN IP Design Example x
2.2.1. Simulating the O-RAN Design Example for Intel Agilex F-Tile Devices 2.2.2. Enabling Dynamic Reconfiguation to the Ethernet IP 2.2.3. O-RAN IP Design Example Testbench
2.3. Operating the O-RAN IP Design Example x
2.3.1. Generating and Downloading the Programming .elf File
1. About the O-RAN Intel® FPGA IP Design Example
2. Getting Started with the O-RAN Intel® FPGA IP Design Example
3. O-RAN Intel® FPGA IP Design Example Functional Description
4. O-RAN IP Design Example User Guide Archives
5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide

3. O-RAN Intel® FPGA IP Design Example Functional Description

Figure 17. Block Diagram
Signal Direction Comments
clk100 Input

Input clock for reconfiguration.

For Intel® Arria® 10 designs, a 156.25 MHz oscillator on the board drives this clock.

For Intel® Agilex™ and Intel® Stratix® 10 designs, a 100 MHz oscillator on the board drives this clock.

mgmt_reset_n Input Input reset for the Nios® II system.
clk_ref Input

For Intel® Arria® 10 designs, a 322.265625 MHz clock input for the Transceiver ATX PLL and 1G/10GbE and 10GBase-KR PHY IP . Connect to pll_refclk0[0]in the Transceiver ATX PLL and rx_cdr_ref_clk_10g[0] in the 1G/10GbE and 10GBase-KR PHY IP.

For Intel® Agilex™ F-tile, Intel® Agilex™ E-tile, and Intel® Stratix® 10 E-tile designs, 156.25 MHz clock input for the E-tile Ethernet Hard IP core. Connect to i_clk_ref[0] in the Ethernet Hard IP.

For Intel® Stratix® 10 H-tile designs, a 322.265625 MHz clock input for the Transceiver ATX PLL and 25G Ethernet IP. Connect to pll_refclk0[0]in the Transceiver ATX PLL and clk_ref[0] in 25G Ethernet IP.

tod_sync_sampling_clk Input

For Intel® Arria® 10 designs, a 250 MHz clock input for TOD subsystem.

tx_serial Output Transmitter serial data. Supports up to four channels.
rx_serial Input Receiver serial data. Supports up to four channels.

O-RAN IP

The O-RAN IP receives and transmits data at the transmitter and receiver application interfaces (the traffic components instantiated within the test wrapper).

eCPRI IP

The eCPRI IP receives and transmits data at the Avalon® streaming source and sink interfaces (from the O-RAN transmitter, and receiver transport interfaces) and the external source and sink interfaces (the external traffic components instantiated within the test wrapper). The eCPRI IP prioritizes the data for transmission to the Ethernet IP.

eCPRI IOPLL

For design examples targeting Intel® Stratix® 10 and Intel® Agilex™ devices only, the eCPRI IOPLL generates the clock output of 390.625 MHz to feed into the transmitter and receiver data path of the eCPRI IP, the O-RAN IP, and the traffic generator and checker components.

PTP IOPLL

For Intel® Arria® 10 devices the PTP IOPLL generates the 312.5 MHz and 156.25 MHz clock inputs for the Low Latency Ethernet 10G MAC, eCPRI, O-RAN, 1G/10GbE and 10GBase-KR PHY IPs.

For Intel® Stratix® 10 devices, the PTP IOPLL generates the latency measurement input reference clock for the 25G Ethernet Intel FPGA IP and the sampling clock for TOD subsystem. For the 25G Ethernet Intel FPGA IP with the IEEE 1588v2 feature, Intel recommends that you set the frequency of this clock to 156.25 MHz.

For more information, refer to the 25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide and the Intel Stratix 10 H-Tile Transceiver PHY User Guide.

Nios II subsystem

The Nios II subsystem consists of the:

  • Avalon memory-mapped bridge, which allows Avalon memory-mapped data arbitration between traffic from the Nios II processor and the test wrapper
  • A Nios II processor
  • An Avalon memory-mapped address decoder

For design examples targeting Intel® Stratix® 10 and Intel® Agilex™ E-tile devices only, the Nios II processor performs the data rate switching based on the output from the test wrapper's rate_switch register value. The Nios II processor programs the necessary register after the command from the test wrapper. Design examples targeting Intel® Arria® 10 devices do not support data rate switching.

Ethernet IP

The design example instantiates one of the following Ethernet IP to interface with the eCPRI IP:

  • Low Latency Ethernet 10G MAC IP and 1G/10GbE and 10GBase-KR PHY IP ( Intel® Arria® 10 designs)
  • Ethernet Hard IP ( Intel® Stratix® 10 E-tile and Intel® Agilex™ designs)
  • 25G Ethernet Stratix 10 IP ( Intel® Stratix® 10 H-tile designs)

TOD Subsystem

The time of day (TOD) subsystem consists of two IEEE 1588 TOD modules for both transmitter and receiver, and one IEEE 1588 TOD synchronizer module.

System Console Access through JTAG Interface

The system console provides an interface for you to debug and monitor the status of the IP and the traffic generators and checkers.

Test Wrapper

The test wrapper consists of numerous traffic generators and checkers that generate different types of data packets to the O-RAN IP and the eCPRI IP.

Test Wrapper O-RAN IP Data Packets

The traffic generator supports O-RAN packets to the Avalon streaming source and sink interfaces of the O-RAN IP with configurations for C-plane, C-plane extension, and U-plane.

Table 4.  C-Plane Configurations
Parameter Description

rtcid

seqid

Transport header fixed parameter value.

dataDirection

Filterindex

Common Header fixed parameter value.

frameId Fixed initial value (configured with parameter).
subframeId Fixed initial value (configured with parameter).
slotId Fixed initial value (configured with parameter).
symbolId Fixed initial value (configured with parameter).

NumberofSections

6 for Sectiontype. 1, 2 for Sectiontype 3.

Sectiontype

1, 3.

Timeoffset

Fixed parameter value.

frameStructure

Fixed parameter value.

cpLength

Fixed parameter value.

udCompHdr

Applicable only when compression is enabled: udCompMeth = 0001 or 0011, and udIqWidth = 1000 or 1100
sectionId Section header fixed parameter value.

Sectiontype

Section extension.
ExtType 3 (DL precoding).
Rb Fixed parameter value.
StartPrb Fixed parameter value.
numPrb Fixed parameter value.

reMask

Fixed parameter value.

numSymbol

Fixed parameter value.

Ef

0 for Sectiontype 1, 1 for Sectiontype 3.

frequencyOffset

Fixed parameter value.
Table 5.  C-Plane Extension Configurations
Parameter Description
NumberofSections 2.
ExtType 3 (DL Precoding).
Payload Size 32 bytes (16 bytes for each section).
Table 6.  U-Plane Configurations
  • Incremental pattern mode generation with some interpacket gaps.
  • Configurable via CSR to run in either non-continuous or continuous mode.
  • Transmitter and receiver packet statistic status available to access via CSR.
Parameter Description

dataDirection

Filterindex

Common header fixed parameter value.
frameId Fixed initial counter value (configured from parameter).
subframeId Fixed initial counter value (configured from parameter).
slotId Fixed initial counter value (configured from parameter).
symbolId Fixed initial counter value (configured from parameter).
udCompHdr Applicable only when compression is enabled. udCompMeth = 0001 or 0011 and udIqWidth = 1000 or 1100
sectionId Section header fixed parameter value.
Rb Fixed parameter value.
StartPrb Fixed parameter value.
numPrb Fixed parameter value.
Table 7.  Supported C and U-plane Traffic Configurations

The table shows specific configuration settings supported in the design example. You may modify these parameters in the generated oran_ed_top.sv and oran_tb.sv files to run the design example successfully.

ENABLE_COMPRESSION1 3 ENABLE_CPLANE2 ENABLE_UPLANE udCompMeth 3 udIqWidth3 C_Sectiontype4
1 1 0 0,1,3 8,12,16 1,3
1 1 1 1,3 8,12 1,3
0 0 1 0 16 1,3
0 1 1 0 16 1,3
0 1 0 0 16 1,3

Test Wrapper ECPRI IP IP Data Packets

For PTP synchronization packets and non-PTP miscellaneous packets to the external source and sink interfaces:

  • External PTP packets:
    • Static Ethernet header generation with predefined parameters: EtherType = 0x88F7, or Message Type = Opcode 0 (sync), or PTP version = 0
    • Predefined pattern mode generation with interpacket gap of two cycles and payload size of 57 bytes for each packet.
    • 128 packets generate every second.
    • CSR configurable to run either non-continuous or continuous.
    • Transmitter or receiver packet statistic status available via CSR.

  • External non-PTP miscellaneous packets:
    • Static Ethernet header generation with predefined parameters: EtherType = 0x8100 (non-PTP)
    • PRBS pattern mode generation with interpacket gap of two cycles and payload size of 128 bytes for each packet.
    • CSR configurable to run either non-continuous or continuous.
    • Transmitter or receiver packet statistic status available via CSR.

Design Example Address Mapping

Table 8.  JTAG to Avalon Memory-mapped Bridge Address Mapping
Address Target
0x20100000 – 0x201fffff 5 IOPLL reconfiguration Avalon memory-mapped register.
0x20200000 – 0x203fffff Ethernet MAC Avalon memory-mapped register.
0x20400000 – 0x205fffff Ethernet MAC Native PHY Avalon memory-mapped register..
0x20600000 – 0x207fffff 5 Native PHY RSFEC Avalon memory-mapped register.
0x40000000 – 0x5fffffff eCPRI IP Avalon memory-mapped register.
0x80000000 – 0x9fffffff Design example test generator and verifier Avalon memory-mapped register.
Table 9.  Address mapping when accessing through the Nios II processorOnly available for Intel® Stratix® 10 designs.
Address Target
0x00100000 – 0x001fffff IOPLL Re-configuration Avalon memory-mapped register
0x00200000 – 0x003fffff Ethernet MAC Avalon memory-mapped register
0x00400000 – 0x005fffff Ethernet MAC Native PHY Avalon memory-mapped register.
0x00600000 – 0x007fffff Native PHY Reed-Solomon FEC Avalon memory-mapped register.

Access the Ethernet MAC and the Ethernet MAC Native PHY Avalon memory-mapped register using word offset instead of byte offset.

For more information on the Ethernet MAC, Ethernet MAC Native PHY Avalon memory-mapped, and eCPRI IP Avalon memory-mapped registers, refer to the respective user guides.

Table 10.  Test generator and verifier Avalon memory-mapped register
Word Offset Description Default Attribute
0x0

Start send data

  • Bit 1: PTP, non-PTP type
  • Bit 0: O-RAN C-plane, U-plane, C-plane extension
 0x0 RW
0x1 Continuous packet enable 0x0 RW
0x2 Clear error 0x0 RW
0x3 6

Rate switch

  • Bit 7: tile
    • 1’b0: H-Tile
    • 1’b1: E-Tile
  • Bit 6:4: Ethernet rate
    • 3’b0: 25G to 10G
    • 3’b1: 10G to 25G
  • Bit 0: switch rate enable

You must set bit 0 and poll until bit 0 is clear for rate switching

E-tile:

0x80

Non E-tile:

0x0

 RW
0x4 6

Rate switch done

  • Bit 1: rate switch done
 0x0 RO
0x5

System configuration status

  • Bit 31: System ready
  • Bit 30-13: Reserved
  • Bit 12-5: UDCOMPPARAM
  • Bit 4: COMP_EN
  • Bit 3: EXT_PACKET_EN
  • Bit 2: CPLANE_EXT_EN
  • Bit 1: CPLANE_EN
  • Bit 0: UPLANE_EN
 0x0 RO
0x6 - 0x1F Reserved 0x0 RO
0x20 eCPRI error interrupt 0x0 RO
0x21 External packets error 0x0 RO
0x22 External PTP packets transmitter SOP count 0x0 RO
0x23 External PTP packets transmitter EOP count 0x0 RO
0x24 External misc packets transmitter SOP count 0x0 RO
0x25 External misc packets transmitter EOP count 0x0 RO
0x26 External receiver packets SOP count 0x0 RO
0x27 External receiver packets EOP count 0x0 RO
0x28 External error count 0x0 RO
0x29 – 0x2C Reserved 0x0 RO
0x2D External PTP timestamp fingerprint error Count 0x0 RO
0x2E External PTP timestamp fingerprint error 0x0 RO
0x2F External receiver error status 0x0 RO
0x30 – 0x53 Reserved 0x0 RO
0x54 O-RAN error interrupt 0x0 RO
0x55

Avalon streaming receiver U-plane error status

  • Bit 0: Avalon streaming receiver U-plane error status
 0x0 RO
0x56

Avalon streaming receiver C-plane error status

  • Bit 0: Avalon streaming receiver C-plane error status
 0x0 RO
0x57

Avalon streaming receiver C-plane extension error status

Bit 0: Avalon streaming receivers C-plane extension error status

 0x0 RO
0x58 C-plane Checker Errors 0x0 RO
0x59 C-plane Checker Errors 0x0 RO
0x60 Transmitter C-plane SOP Count 0x0 RO
0x61 Transmitter C-plane EOP Count 0x0 RO
0x62 Receiver C-plane SOP Count 0x0 RO
0x63 Receiver C-plane EOP Count 0x0 RO
0x64 Total C-plane Error Count 0x0 RO
0x65 C-plane Extension Checker Errors 0x0 RO
0x66 Transmitter C-plane extension SOP count 0x0 RO
0x67 Transmitter C-plane extension EOP Count 0x0 RO
0x68 Receiver C-plane extension SOP Count 0x0 RO
0x69 Receiver C-plane extension EOP count 0x0 RO
0x70 Transmitter C-plane extension error count 0x0 RO
0x71 Transmitter U-plane SOP count 0x0 RO
0x72 Transmitter U-plane EOP count 0x0 RO
0x73 U-plane checker errors 0x0 RO
0x74 Receiver U-plane SOP count 0x0 RO
0x75 Receiver U-plane EOP count 0x0 RO
0x76 Total U-plane error count 0x0 RO
Related Information
1 This parameter setting must match Enable companding in the O-RAN IP GUI.
2 These parameter settings are only applicable when you turn on Enable C-plane in the O-RAN IP GUI. When you turn off Enable C-Plane, you must set the following configuration:
  • ENABLE_CPLANE = 0
3 These parameter settings are only applicable when you turn on Enable companding in the O-RAN IP GUI. when you turn off Enable companding, you must set the following configurations:
  • ENABLE_COMPRESSION = 0
  • udCompMeth = 0
  • udIqWidth = 16
4 The design example ignores the C_Sectiontype parameter when you turn off Enable C-plane in the O-RAN IP GUI
  • For C_Sectiontype = 1, the example design only supports C_NumberofSections = 6.
  • For C_Sectiontype = 3, the example design only supports C_NumberofSections = 2.
.
5 Only available for Intel® Stratix® 10 and Intel® Agilex™ E-tile designs.
6 Only available for Intel® Stratix® 10 and Intel® Agilex™ E-tile designs.
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