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1. About This IP Core
2. Getting Started With the 50G Interlaken IP Core
3. 50G Interlaken IP Core Parameter Settings
4. Functional Description
5. 50G Interlaken IP core Signals
6. 50G Interlaken IP Core Register Map
7. 50G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 50G Interlaken IP core
10. 50G Interlaken Intel® FPGA IP User Guide Archives
11. Document Revision History for 50G Interlaken Intel® FPGA IP User Guide
A. Performance and Fmax Requirements for 40G Ethernet Traffic
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Specifying the 50G Interlaken IP Core Parameters and Options
2.3. Files Generated for Arria V GZ and Stratix V Variations
2.4. Files Generated for Intel® Arria® 10 Variations
2.5. Simulating the 50G Interlaken IP Core
2.6. Integrating Your IP Core in Your Design
2.7. Compiling the Full Design and Programming the FPGA
2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
5.1. 50G Interlaken IP Core Clock Interface Signals
5.2. 50G Interlaken IP Core Reset Interface Signals
5.3. 50G Interlaken IP Core User Data Transfer Interface Signals
5.4. 50G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals
5.5. 50G Interlaken IP Core Management Interface
5.6. Device Dependent Signals
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1.1. Features
The 50G Interlaken IP core has the following features:
- Compliant with the Interlaken Protocol Specification, Revision 1.2.
- Supports eight serial lanes in configurations that provide up to 50 Gbps raw bandwidth.
- Supports per‑lane data rate of 6.25 Gbps using Intel® on‑chip high‑speed transceivers.
- Supports dynamically configurable BurstMax and BurstMin values.
- Supports Packet mode and Interleaved (Segmented) mode for user data transfer.
- Supports up to 256 logical channels in out‑of‑the‑box configuration.
- Supports optional user‑controlled in‑band flow control with 1, 2, 4, 8, or 16 16‑bit calendar pages.
- Supports optional out‑of‑band flow control blocks.
Section Content
IP Core Supported Combinations of Number of Lanes and Data Rate
IP Core Raw Aggregate Bandwidth
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