50G Interlaken Intel® FPGA IP User Guide

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ID 683217
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This IP Core 2. Getting Started With the 50G Interlaken IP Core 3. 50G Interlaken IP Core Parameter Settings 4. Functional Description 5. 50G Interlaken IP core Signals 6. 50G Interlaken IP Core Register Map 7. 50G Interlaken IP Core Test Features 8. Advanced Parameter Settings 9. Out-of-Band Flow Control in the 50G Interlaken IP core 10. 50G Interlaken Intel® FPGA IP User Guide Archives 11. Document Revision History for 50G Interlaken Intel® FPGA IP User Guide A. Performance and Fmax Requirements for 40G Ethernet Traffic
1. About This IP Core x
1.1. Features 1.2. Device Family Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Device Speed Grade Support 1.6. Release Information
1.1. Features x
1.1.1. IP Core Supported Combinations of Number of Lanes and Data Rate 1.1.2. IP Core Raw Aggregate Bandwidth
2. Getting Started With the 50G Interlaken IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 50G Interlaken IP Core Parameters and Options 2.3. Files Generated for Arria V GZ and Stratix V Variations 2.4. Files Generated for Intel® Arria® 10 Variations 2.5. Simulating the 50G Interlaken IP Core 2.6. Integrating Your IP Core in Your Design 2.7. Compiling the Full Design and Programming the FPGA 2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignments 2.6.2. Transceiver Logical Channel Numbering 2.6.3. Adding the Reconfiguration Controller 2.6.4. Adding the External PLL
2.6.3. Adding the Reconfiguration Controller x
2.6.3.1. Generating the Reconfiguration Controller 2.6.3.2. Connecting the Reconfiguration Controller to the IP Core
3. 50G Interlaken IP Core Parameter Settings x
3.1. Meta Frame Length in Words 3.2. Enable Native PHY Debug Master Endpoint (NPDME) 3.3. Transceiver Reference Clock Frequency 3.4. Number of Calendar Pages 3.5. TX Scrambler Seed 3.6. Transfer Mode Selection
4. Functional Description x
4.1. Interfaces Overview 4.2. High Level Block Diagram 4.3. Clocking and Reset Structure for IP Core 4.4. Interleaved and Packet Modes 4.5. 50G Interlaken IP Core Transmit Path 4.6. 50G Interlaken IP Core Receive Path
4.1. Interfaces Overview x
4.1.1. Application Interface 4.1.2. Interlaken Interface 4.1.3. Out‑of‑Band Flow Control Interface 4.1.4. Management Interface 4.1.5. Transceiver Control Interfaces
4.1.5. Transceiver Control Interfaces x
4.1.5.1. Transceiver Reconfiguration Controller Interface 4.1.5.2. Intel® Arria® 10 External PLL Interface 4.1.5.3. Intel® Arria® 10 Transceiver Reconfiguration Interface
4.3. Clocking and Reset Structure for IP Core x
4.3.1. 50G Interlaken IP Core Clock Signals 4.3.2. IP Core Reset 4.3.3. IP Core Reset Sequence with the Reconfiguration Controller
4.5. 50G Interlaken IP Core Transmit Path x
4.5.1. 50G Interlaken IP Core Transmit User Data Interface Examples 4.5.2. 50G Interlaken IP Core In-Band Calendar Bits on Transmit Side 4.5.3. 50G Interlaken IP Core Transmit Path Blocks
4.5.1. 50G Interlaken IP Core Transmit User Data Interface Examples x
4.5.1.1. 50G Interlaken IP Core Interleaved Mode (Segmented Mode) Example 4.5.1.2. 50G Interlaken IP Core Packet Mode Operation Example 4.5.1.3. 50G Interlaken IP Core Back-Pressured Packet Transfer Example
4.5.3. 50G Interlaken IP Core Transmit Path Blocks x
4.5.3.1. 50G Interlaken IP Core TX Transmit Buffer 4.5.3.2. 50G Interlaken IP Core TX MAC 4.5.3.3. 50G Interlaken IP Core TX PCS 4.5.3.4. 50G Interlaken IP Core TX PMA
4.6. 50G Interlaken IP Core Receive Path x
4.6.1. 50G Interlaken IP Core Receive User Data Interface Examples 4.6.2. 50G Interlaken IP Core RX Errored Packet Handling 4.6.3. In-Band Calendar Bits on the 50G Interlaken IP Core Receiver User Data Interface 4.6.4. 50G Interlaken IP Core Receive Path Blocks
4.6.1. 50G Interlaken IP Core Receive User Data Interface Examples x
4.6.1.1. 50G Interlaken IP Core Receiver Side Example
4.6.2. 50G Interlaken IP Core RX Errored Packet Handling x
4.6.2.1. 50G Interlaken IP Core Receiver Side Example With Errors and In-Band Calendar Bits
4.6.4. 50G Interlaken IP Core Receive Path Blocks x
4.6.4.1. 50G Interlaken IP Core RX PMA 4.6.4.2. 50G Interlaken IP Core RX PCS 4.6.4.3. 50G Interlaken IP Core RX MAC 4.6.4.4. 50G Interlaken IP Core RX Regroup Block
5. 50G Interlaken IP core Signals x
5.1. 50G Interlaken IP Core Clock Interface Signals 5.2. 50G Interlaken IP Core Reset Interface Signals 5.3. 50G Interlaken IP Core User Data Transfer Interface Signals 5.4. 50G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals 5.5. 50G Interlaken IP Core Management Interface 5.6. Device Dependent Signals
5.6. Device Dependent Signals x
5.6.1. Transceiver Reconfiguration Controller Interface Signals 5.6.2. Intel® Arria® 10 External PLL Interface Signals 5.6.3. Intel® Arria® 10 Transceiver Reconfiguration Interface Signals
7. 50G Interlaken IP Core Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode 7.3. PRBS Generation and Validation 7.4. CRC32 Error Injection
7.3. PRBS Generation and Validation x
7.3.1. Setting up PRBS Mode in Arria V and Stratix V Devices 7.3.2. Setting up PRBS Mode in Intel® Arria® 10 Devices
8. Advanced Parameter Settings x
8.1. Hidden Parameters 8.2. Modifying Hidden Parameter Values
8.1. Hidden Parameters x
8.1.1. Required User Clock Frequency 8.1.2. Counter Reset Bits 8.1.3. Include Temp Sense 8.1.4. RXFIFO Address Width 8.1.5. SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping) 8.1.6. Use ATX or CMU PLL 8.1.7. Lane Profile
9. Out-of-Band Flow Control in the 50G Interlaken IP core x
9.1. Out-of-Band Flow Control Block Clocks 9.2. TX Out‑of‑Band Flow Control Signals 9.3. RX Out-of-Band Flow Control Signals
1. About This IP Core
2. Getting Started With the 50G Interlaken IP Core
3. 50G Interlaken IP Core Parameter Settings
4. Functional Description
5. 50G Interlaken IP core Signals
6. 50G Interlaken IP Core Register Map
7. 50G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 50G Interlaken IP core
10. 50G Interlaken Intel® FPGA IP User Guide Archives
11. Document Revision History for 50G Interlaken Intel® FPGA IP User Guide
A. Performance and Fmax Requirements for 40G Ethernet Traffic

5.3. 50G Interlaken IP Core User Data Transfer Interface Signals

Table 13.   50G Interlaken IP Core User Data Transfer Interface

Signal Name

Direction

Width (Bits)

Description

50G Interlaken IP Core Transmit User Interface

itx_chan

Input

8

Transmit logic channel number. The IP core supports up to 256 channels. The 50G Interlaken IP core samples this value only when itx_sop or itx_sob is high and itx_num_valid has a non-zero value.

itx_num_valid

Input

3

itx_num_valid[2:0] specifies the number of valid 64-bit words in the current packet in the current data symbol. The maximum value of itx_num_valid[2:0] is four, because a data symbol on the 256 bit wide data path has four words (4 x 64 bits = 256 bits).

In non-valid cycles, you must set the value of itx_num_valid[2:0] to zero.

In valid cycles, you must set the value of itx_num_valid[2:0] as follows:

  • 3’b100: if all four words contain valid data from the current packet.
  • 3’b0xx: where xx indicates the number of valid words that are part of the current packet, if the number is less than four. Data is always MSB aligned (left aligned). For example, the value of 3’b011 indicates that word 0 (bit [63:0]) is not valid.

You must set the value of itx_num_valid to zero in all non-valid cycles, even when itx_ready is not asserted.

itx_sop

Input

1

Indicates the current data symbol on itx_din_words contains the start of a packet (SOP). This signal has the following valid values:

  • 1'b0—The current data symbol does not contain the start of a packet.
  • 1'b1—The current data symbol contains the start of a packet.

itx_eopbits

Input

4

Indicates whether the current data symbol contains the end of a packet (EOP) with or without an error, and specifies the number of valid bytes in the current end-of-packet, non-error 8-byte data word, if relevant.

You must set the value of itx_eopbits as follows:

  • 4b’0000: no end of packet, no error.
  • 4b’0001: Error and end of packet.
  • 4b’1xxx: End of packet. xxx indicates the number of valid bytes in the final valid 8-byte word of the packet, as follows:
    • 3b’000: all 8 bytes are valid.
    • 3b’001: 1 byte is valid.
    • ...
    • 3b’111: 7 bytes are valid.

All other values (4'b01xx, 4'b001x) are undefined.

The valid bytes always start in bit positions [63:56] of the final valid data word of the packet.

itx_sob

Input

1

Indicates the current data symbol contains the start of a burst (SOB). If the 50G Interlaken IP core is in Interleaved mode, you are responsible for providing this start of the burst signal. If the50G Interlaken IP core is in Packet mode, the IP core ignores this signal. The 50G Interlaken IP core samples the itx_chan signal during this cycle.

This signal has the following valid values:

  • 1'b0—The current data symbol does not contain the start of a burst.
  • 1'b1—The current data symbol contains the start of a burst.

Typically, you use this mode for sending interleaved packets. However, you can still send non-interleaved packets as long as you provide the itx_sob and itx_eob signal values. You are responsible to comply with the BurstMax and BurstMin parameters. If the burst you send is too large, it can overflow the 50G Interlaken transmit buffer.

itx_eob

Input

1

End of the burst. If the 50G Interlaken IP core is in Interleaved mode, you are responsible for providing this end of the burst signal. If the 50G Interlaken IP core is in Packet mode, the IP core ignores this signal. You are responsible to comply with the BurstMax and BurstMin parameters.

itx_din_words

Input

256

The four 64-bit words of input data (one data symbol). When itx_num_valid has the value of zero, the IP core ignores itx_din_words.

itx_calendar

Input

16 N

Multiple pages (16 bits per page) of calendar input bits. The 50G Interlaken IP Core copies these bits to the in-band flow control bits in N control words that it sends on the Interlaken link. N is the value of the Number of calendar pages parameter, which can be any of 1, 2, 4, 8. or 16. This signal is synchronous with tx_usr_clk, although it is not part of the user data transfer protocol.

itx_ready

Output

1

Flow control signal to back pressure transmit traffic. When this signal is high, you can send traffic to the IP core. When this signal is low, you should stop sending traffic to the IP core within one to four cycles.

You can consider the inverse of itx_ready to be a FIFO-almost-full indicator. In full duplex mode, itx_ready is low when rx_lanes_aligned is low.

itx_ifc_err

Output

1

Indicates the transmit side user data transfer interface received traffic that the 50G Interlaken IP Core does not support. The IP core asserts the itx_ifc_err signal in the following cases:
  • In Interleaved mode, the IP core receives a burst that exceeds the size of MaxBurst.
  • Two instances of non-zero itx_sop (a start of packet), or two instances of non-zero itx_sob (a start of burst), are separated by fewer than 64 bytes.

The IP core asserts the itx_ifc_err signal for a single clock cycle. The signal pulses within the current burst, with a delay of one or two cycles after the error on the transmit side user data transfer interface.

50G Interlaken IP Core Receive User Interface

irx_chan

Output

8

Receive logic channel number. The IP core supports up to 256 channels. You should sample this value when irx_sop or irx_sob is high and irx_num_valid has a non-zero value.

irx_num_valid

Output

3

irx_num_valid[2:0] specifies the number of valid 64-bit words in the current packet in the current data symbol. The maximum value of irx_num_valid[2:0] is four, because a data symbol on the 256 bit wide data path has four words (4 x 64 bits = 256 bits).

In valid cycles, the IP core sets the value of irx_num_valid[2:0] as follows:

  • 3’b100: if all four words contain valid data from the current packet.
  • 3’b0xx: where xx indicates the number of valid words that are part of the current packet, if the number is less than four. Data is always MSB aligned (left aligned). For example, the value of 3’b011 indicates that word 0 (bit [63:0]) is not valid.

The IP core sets the value of irx_num_valid to zero in all non-valid cycles.

irx_sop

Output

1

Indicates the current data symbol on irx_dout_words contains the start of a packet (SOP). This signal has the following valid values:

  • 1'b0—The current data symbol does not contain the start of a packet.
  • 1'b1—The current data symbol contains the start of a packet.

irx_eopbits

Output

4

Indicates whether the current data symbol contains the end of a packet (EOP) with or without an error, and specifies the number of valid bytes in the current end-of-packet, non-error 8-byte data word, if relevant.

The IP core sets the value of irx_eopbits as follows:

  • 4b’0000: no end of packet, no error.
  • 4b’0001: Error and end of packet.
  • 4b’1xxx: End of packet. xxx indicates the number of valid bytes in the final valid 8-byte word of the packet, as follows:
    • 3b’000: all 8 bytes are valid.
    • 3b’001: 1 byte is valid.
    • ...
    • 3b’111: 7 bytes are valid.

All other values (4'b01xx, 4'b001x) are undefined and are not generated by the IP core.

The valid bytes always start in bit positions [63:56] of the final valid data word of the packet.

irx_sob

Output

1

Start of the burst. The 50G Interlaken IP core indicates the start of the burst. The signal irx_channel is only valid when irx_sob is high. This signal toggles in Packet Mode and in Interleaved Mode.

This signal has the following valid values:

  • 1'b0—The current data symbol does not contain the start of a burst.
  • 1'b1—The current data symbol contains the start of a burst.

irx_eob

Output

1

End of the burst. The 50G Interlaken IP core indicates the end of the burst. This signal toggles in Packet Mode and in Interleaved Mode.

irx_dout_words

Output

256

The four 64-bit words of output data (one data symbol). When irx_num_valid has the value of zero, you should ignore irx_dout_words.

irx_calendar

Output

16 × N

Multiple pages (16 bits per page) of calendar output bits. The value is the in-band flow control bits from N control words on the incoming Interlaken link. N is the value of the Number of calendar pages parameter, which can be any of 1, 2, 4, 8, or 16. This signal is synchronous with rx_usr_clk, although it is not part of the user data transfer protocol.

irx_err

Output

1

Indicates an errored packet. This signal is valid only when both irx_num_valid[2:0] and irx_eopbits[3:0] are non-zero.

When a CRC24 or other error occurs, the 50G Interlaken IP core asserts this signal for all open channel packets to label them all as errored packets, because the IP core cannot assign the error to a specific channel.

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