50G Interlaken Intel® FPGA IP User Guide

Download PDF
ID 683217
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This IP Core 2. Getting Started With the 50G Interlaken IP Core 3. 50G Interlaken IP Core Parameter Settings 4. Functional Description 5. 50G Interlaken IP core Signals 6. 50G Interlaken IP Core Register Map 7. 50G Interlaken IP Core Test Features 8. Advanced Parameter Settings 9. Out-of-Band Flow Control in the 50G Interlaken IP core 10. 50G Interlaken Intel® FPGA IP User Guide Archives 11. Document Revision History for 50G Interlaken Intel® FPGA IP User Guide A. Performance and Fmax Requirements for 40G Ethernet Traffic
1. About This IP Core x
1.1. Features 1.2. Device Family Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Device Speed Grade Support 1.6. Release Information
1.1. Features x
1.1.1. IP Core Supported Combinations of Number of Lanes and Data Rate 1.1.2. IP Core Raw Aggregate Bandwidth
2. Getting Started With the 50G Interlaken IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 50G Interlaken IP Core Parameters and Options 2.3. Files Generated for Arria V GZ and Stratix V Variations 2.4. Files Generated for Intel® Arria® 10 Variations 2.5. Simulating the 50G Interlaken IP Core 2.6. Integrating Your IP Core in Your Design 2.7. Compiling the Full Design and Programming the FPGA 2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignments 2.6.2. Transceiver Logical Channel Numbering 2.6.3. Adding the Reconfiguration Controller 2.6.4. Adding the External PLL
2.6.3. Adding the Reconfiguration Controller x
2.6.3.1. Generating the Reconfiguration Controller 2.6.3.2. Connecting the Reconfiguration Controller to the IP Core
3. 50G Interlaken IP Core Parameter Settings x
3.1. Meta Frame Length in Words 3.2. Enable Native PHY Debug Master Endpoint (NPDME) 3.3. Transceiver Reference Clock Frequency 3.4. Number of Calendar Pages 3.5. TX Scrambler Seed 3.6. Transfer Mode Selection
4. Functional Description x
4.1. Interfaces Overview 4.2. High Level Block Diagram 4.3. Clocking and Reset Structure for IP Core 4.4. Interleaved and Packet Modes 4.5. 50G Interlaken IP Core Transmit Path 4.6. 50G Interlaken IP Core Receive Path
4.1. Interfaces Overview x
4.1.1. Application Interface 4.1.2. Interlaken Interface 4.1.3. Out‑of‑Band Flow Control Interface 4.1.4. Management Interface 4.1.5. Transceiver Control Interfaces
4.1.5. Transceiver Control Interfaces x
4.1.5.1. Transceiver Reconfiguration Controller Interface 4.1.5.2. Intel® Arria® 10 External PLL Interface 4.1.5.3. Intel® Arria® 10 Transceiver Reconfiguration Interface
4.3. Clocking and Reset Structure for IP Core x
4.3.1. 50G Interlaken IP Core Clock Signals 4.3.2. IP Core Reset 4.3.3. IP Core Reset Sequence with the Reconfiguration Controller
4.5. 50G Interlaken IP Core Transmit Path x
4.5.1. 50G Interlaken IP Core Transmit User Data Interface Examples 4.5.2. 50G Interlaken IP Core In-Band Calendar Bits on Transmit Side 4.5.3. 50G Interlaken IP Core Transmit Path Blocks
4.5.1. 50G Interlaken IP Core Transmit User Data Interface Examples x
4.5.1.1. 50G Interlaken IP Core Interleaved Mode (Segmented Mode) Example 4.5.1.2. 50G Interlaken IP Core Packet Mode Operation Example 4.5.1.3. 50G Interlaken IP Core Back-Pressured Packet Transfer Example
4.5.3. 50G Interlaken IP Core Transmit Path Blocks x
4.5.3.1. 50G Interlaken IP Core TX Transmit Buffer 4.5.3.2. 50G Interlaken IP Core TX MAC 4.5.3.3. 50G Interlaken IP Core TX PCS 4.5.3.4. 50G Interlaken IP Core TX PMA
4.6. 50G Interlaken IP Core Receive Path x
4.6.1. 50G Interlaken IP Core Receive User Data Interface Examples 4.6.2. 50G Interlaken IP Core RX Errored Packet Handling 4.6.3. In-Band Calendar Bits on the 50G Interlaken IP Core Receiver User Data Interface 4.6.4. 50G Interlaken IP Core Receive Path Blocks
4.6.1. 50G Interlaken IP Core Receive User Data Interface Examples x
4.6.1.1. 50G Interlaken IP Core Receiver Side Example
4.6.2. 50G Interlaken IP Core RX Errored Packet Handling x
4.6.2.1. 50G Interlaken IP Core Receiver Side Example With Errors and In-Band Calendar Bits
4.6.4. 50G Interlaken IP Core Receive Path Blocks x
4.6.4.1. 50G Interlaken IP Core RX PMA 4.6.4.2. 50G Interlaken IP Core RX PCS 4.6.4.3. 50G Interlaken IP Core RX MAC 4.6.4.4. 50G Interlaken IP Core RX Regroup Block
5. 50G Interlaken IP core Signals x
5.1. 50G Interlaken IP Core Clock Interface Signals 5.2. 50G Interlaken IP Core Reset Interface Signals 5.3. 50G Interlaken IP Core User Data Transfer Interface Signals 5.4. 50G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals 5.5. 50G Interlaken IP Core Management Interface 5.6. Device Dependent Signals
5.6. Device Dependent Signals x
5.6.1. Transceiver Reconfiguration Controller Interface Signals 5.6.2. Intel® Arria® 10 External PLL Interface Signals 5.6.3. Intel® Arria® 10 Transceiver Reconfiguration Interface Signals
7. 50G Interlaken IP Core Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode 7.3. PRBS Generation and Validation 7.4. CRC32 Error Injection
7.3. PRBS Generation and Validation x
7.3.1. Setting up PRBS Mode in Arria V and Stratix V Devices 7.3.2. Setting up PRBS Mode in Intel® Arria® 10 Devices
8. Advanced Parameter Settings x
8.1. Hidden Parameters 8.2. Modifying Hidden Parameter Values
8.1. Hidden Parameters x
8.1.1. Required User Clock Frequency 8.1.2. Counter Reset Bits 8.1.3. Include Temp Sense 8.1.4. RXFIFO Address Width 8.1.5. SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping) 8.1.6. Use ATX or CMU PLL 8.1.7. Lane Profile
9. Out-of-Band Flow Control in the 50G Interlaken IP core x
9.1. Out-of-Band Flow Control Block Clocks 9.2. TX Out‑of‑Band Flow Control Signals 9.3. RX Out-of-Band Flow Control Signals
1. About This IP Core
2. Getting Started With the 50G Interlaken IP Core
3. 50G Interlaken IP Core Parameter Settings
4. Functional Description
5. 50G Interlaken IP core Signals
6. 50G Interlaken IP Core Register Map
7. 50G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 50G Interlaken IP core
10. 50G Interlaken Intel® FPGA IP User Guide Archives
11. Document Revision History for 50G Interlaken Intel® FPGA IP User Guide
A. Performance and Fmax Requirements for 40G Ethernet Traffic

6. 50G Interlaken IP Core Register Map

The 50G Interlaken IP core control registers are 32 bits wide and are accessible to you using the management interface, an Avalon-MM interface which conforms to the Avalon Interface Specifications. This table lists the registers available in the IP core. All unlisted locations are reserved.

Table 19.   50G Interlaken IP Core Register Map

Offset

Name

R/W

Description

9'h0

PCS_BASE

RO

[31:8] – Constant “HSi” ASCII for Arria® V and Stratix® V variants.

[31:8] – Constant “HSj” ASCII for Intel® Arria® 10 variant.

[7:0] – version number

Despite its name, this register does not encode the hard PCS base address.

9'h1

LANE_COUNT

RO

Number of lanes

9'h2

TEMP_SENSE

RO

Device temperature according to the internal temperature sensing diode.

[7:0] – the temperature in degrees Fahrenheit

[15:8] – the temperature in degrees Celsius

For example, when the temperature is 54 degrees Celsius (130 degrees Fahrenheit), the value of the register is 0x3682. To interpret this register value, you read 0x36 (decimal 54) to be the temperature in degrees Celsius, and you read 0x82 (decimal 130) to be the temperature in degrees Fahrenheit.

This register is invalid in the following IP core variations:

  • Variations that target an Intel® Arria® 10 device
  • Variations in which you turn off the hidden parameter Include Temp Sense

9'h3

ELAPSED_SEC

RO

[23:0] - Elapsed seconds since power up. The IP core calculates this value from the management interface clock (mm_clk) for diagnostic purposes. During continuous operation, this value rolls over every 194 days.

9'h4

TX_EMPTY

RO

[NUM_LANES–1:0] – Transmit FIFO status (empty)

9'h5

TX_FULL

RO

[NUM_LANES–1:0] – Transmit FIFO status (full)

9'h6

TX_PEMPTY

RO

[NUM_LANES–1:0] – Transmit FIFO status (partially empty)

9'h7

TX_PFULL

RO

[NUM_LANES–1:0] – Transmit FIFO status (partially full)

9'h8

RX_EMPTY

RO

[NUM_LANES–1:0] – Receive FIFO status (empty)

9'h9

RX_FULL

RO

[NUM_LANES–1:0] – Receive FIFO status (full)

9'hA

RX_PEMPTY

RO

[NUM_LANES–1:0] – Receive FIFO status (partially empty)

9'hB

RX_PFULL

RO

[NUM_LANES–1:0] – Receive FIFO status (partially full)

9'hC

REF_KHZ 1

RO

PLL reference clock frequency (kHz)

9'hD

RX_KHZ 1

RO

RX recovered clock frequency (kHz)

9'hE

TX_KHZ 1

RO

TX serial clock frequency (kHz)

9'hF

LANE_PROFILE

RO

[NUM_LANES–1:0] – Mask delineating the transceivers this IP core uses on the device. For example, if the FPGA has 24 lanes on one side of the device and the IP core uses the bottom eight transceivers, the mask would be 24'b000000_000000_000011_111111. .

This register is not available in IP core variations that target an Intel® Arria® 10 device.

9'h10

PLL_LOCKED

RO

In Intel® Arria® 10 devices: [0] – Transmit PLL lock indication.

In other device families: [Number of transceiver blocks–1:0] – Transceiver block transmit PLL n lock indication. One lock indicator per transceiver block. Bits that correspond to unused transceiver block PLLs are forced to 1.

9'h11

FREQ_LOCKED

RO

[NUM_LANES–1:0] – Clock data recovery is frequency locked on the inbound data stream

9'h12

LOOPBACK

RW

[NUM_LANES–1:0] – For each lane, write a 1 to activate internal TX to RX serial loopback mode, or write a 0 to disable the loopback for normal operation.

9'h13

RESET

RW

Bit 9 : 1 = Force lock to data mode

Bit 8 : 1 =Force lock to reference mode

Bit 7 : 1 = Synchronously clear the TX-side error counters and sticky flags

Bit 6 : 1 = Synchronously clear the RX-side error counters and sticky flags

Bit 5 : 1 =Program load mode: perform a sequence of DMA reads. Currently the IP core supports only the value of 1'b0, indicating a processor controls the read operations.

Bit 4 : 1 = Ignore the RX analog reset

Bit 3 : 1 = Reset the soft microcontroller

Bit 2 : 1 = Reset the transmitter and the receiver

Bit 1 : 1 = Reset the receiver

Bit 0 : 1 =Ignore RX digital resets

The normal operating state for this register is all zeroes, to allow automatic reset control. These bits are intended primarily for hardware debugging use. Bit 2 is a good general purpose soft reset. Bits 6 and 7 are convenient for monitoring long stretches of error-free operation.

9'h20

ALIGN

RO

Bit 12 : TX lanes are aligned

Bit 0 : RX lanes are aligned.

9'h21

WORD_LOCK

RO

[NUM_LANES–1:0] – Word (block) boundaries have been identified in the RX stream.

9'h22

SYNC_LOCK

RO

[NUM_LANES–1:0] – Metaframe synchronization has been achieved.

9'h23

CRC0

RO

4 bit counters indicating CRC errors in lanes 7,6,5,4,3,2,1,0.

These saturate at F, and you clear them by setting bit 6 in the RESET register.

9'h24

CRC1

RO

4 bit counters indicating CRC errors in lanes 15,14,13,12,11,10,9,8.

These will saturate at F, and you clear them by setting bit 6 in the RESET register.

9'h25

CRC2

RO

4 bit counters indicating CRC errors in lanes 23,22,21,20,19,18,17,16.

These will saturate at F, and you clear them by setting bit 6 in the RESET register.

9'h27

SH_ERR

RO

[NUM_LANES–1:0] – Sticky flag indicating a sync header (framing bit) error has occurred in the corresponding RX lane since this bit was last cleared through the RESET register.

9'h28

RX_LOA

RO

Bit [0] – Sticky flag indicating loss of RX side lane-to-lane alignment since this bit was last cleared through the RESET register. Typically, the IP core asserts this bit in case of a catastrophic problem such as one or more lanes going down.

9'h29

TX_LOA

RO

Bit [0] – Sticky flag indicating loss of TX side lane to lane alignment since this bit was last cleared through the RESET register. Typically, the IP core asserts this bit in case of a TX FIFO underflow / overflow caused by a significant deviation from the expected data flow rate through the TX PCS.

9'h30

PCS_6SEL

RO

Transceiver block selection for PCS test bus. (Factory use only).

9'h31

PCS_LNSEL

RO

Lane selection within transceiver block for PCS test bus. (Factory use only).

9'h32

PCS_TB

RO

PCS test bus. (Factory use only).

9'h33

Reserved

9'h34

RX_PRBS_DONE

RO

[NUM_LANES–1:0] – Indicates whether enough bits have been received on the corresponding RX lane for one complete pass through the PRBS polynomial.

9'h35

RX_PRBS_ERR

RO

[NUM_LANES–1:0] – Sticky flag that indicates whether a PRBS error has occurred on the corresponding RX lane after RX_PRBS_DONE has attained the value of 1.

9'h36

RX_PRBS_COUNT

RO

[7:0] – This eight-bit counter holds the number of words that had PRBS errors across all lanes. Saturates at the value of 0xFF.

9'h37

RX_PRBS_CTRL

RW

Bit [0] – If you set this bit to the value of 1, the IP core clears the RX_PRBS_DONE, RX_PRBS_ERR, and RX_PRBS_COUNT registers. Reset this bit to the value of 0 to capture new PRBS status.

9'h38

CRC32_ERR_INJECT

RW

[NUM_LANES–1:0] - When a bit has the value of 1, the IP core injects CRC32 errors on the corresponding TX lane. When it has the value of 0, the IP core does not inject errors on the TX lane. You must maintain each bit at the value of 1 for the duration of a Meta Frame, at least, to ensure that the IP core transmits at least one CRC32 error.

Related Information
1 Intel® recommends that you use this register only during hardware operation. During simulation, you should not rely on the value in this register, because the amount of simulation time required for the IP core to provide consistent values in the REF_KHZ, RX_KHZ, and TX_KHZ registers is too long.
Level Two Title