FIR II IP Intel® FPGA IP: User Guide

ID 683208
Date 9/17/2024
Public
Document Table of Contents

3.4. FIR II IP Core Input and Output Options

Table 11.  Input and Output Options Parameters
Parameter Value Description
Input Options
Input Type Signed Binary

Signed Fractional Binary

Signed binary or signed fractional binary format input data. Select Signed Fractional Binary to monitor which bits the IP core preserves and which bits it removes during the filtering process.
Input Width 1–32 The width of the input data sent to the filter.
Input Fractional Width 0–32 The width of the data input into the filter when you select Signed Fractional Binary as your input data type.
Output Options
Output Type Signed Binary

Signed Fractional Binary

Signed binary or a signed fractional binary format output data. Select Signed Fractional Binary to monitor which bits the IP core preserves and which bits it removes during the filtering process.
Output Width 0–32 The width of the output data (with limited precision) from the filter.
Output Fractional Width 0–32 The width of the output data (with limited precision) from the filter when you select Signed Fractional Binary as your output data.
Output MSB Rounding Truncation/ Saturating Truncate or saturate the most significant bit (MSB).
MSB Bits to Remove 0–32 The number of MSB bits to truncate or saturate. The value must not be greater than its corresponding integer bits or fractional bits.
Output LSB Rounding Truncation/ Rounding Truncate or round the least significant bit (LSB).
LSB Bits to Remove 0–32 The number of LSB bits to truncate or round. The value must not be greater than its corresponding integer bits or fractional bits.