FIR II IP Intel® FPGA IP: User Guide

ID 683208
Date 9/17/2024
Public
Document Table of Contents

3.4.1. Signed Fractional Binary

The FIR II IP core supports two’s complement, signed fractional binary notation, which allows you to monitor which bits the IP core preserves and which bits it removes during filtering. A signed binary fractional number has the format:

<sign> <integer bits>.<fractional bits>

For example, if the number has 3 fractional bits and 4 integer bits plus a sign bit, the entire 8-bit integer number is divided by 8, which gives a number with a binary fractional component.

The total number of bits equals to the sign bits + integer bits + fractional bits. The sign + integer bits is equal to Input Bit WidthInput Fractional Bit Width with a constraint that at least 1 bit must be specified for the sign.

The output data format is defined by::

<sign> <x1 integer bits>.<y1 fractional bits> Original input data

<sign> <x2 integer bits>.<y2 fractional bits> Original coefficient data

<sign> <i integer bits>.<y1 + y2 fractional bits> Full precision after FIR calculation

where i = ceil(log2ceil(number of coefficients/interpolation factor)) + x1 + x2