Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization

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ID 683174
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Power Analysis 2. Power Optimization 3. Power Analysis and Optimization Document Archive A. Quartus® Prime Pro Edition User Guides
1. Power Analysis x
1.1. Power Analysis Tools 1.2. Running the Power Analyzer 1.3. Specifying Power Analyzer Input 1.4. Viewing Power Analysis Reports 1.5. Power Analysis in Modular Design Flows 1.6. Scripting Support 1.7. Power Analysis Revision History
1.3. Specifying Power Analyzer Input x
1.3.1. Settings for Power Analysis 1.3.2. Specifying Signal Activity Data 1.3.3. Specifying the Default Toggle Rate 1.3.4. Specifying Toggle Rates for Specific Nodes 1.3.5. Avoiding Simulation Node Name Match
1.3.2. Specifying Signal Activity Data x
1.3.2.1. Using Simulation Signal Activity Data in Power Analysis 1.3.2.2. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation 1.3.2.3. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities 1.3.2.4. Signal Activities from User Defaults Only
1.3.2.1. Using Simulation Signal Activity Data in Power Analysis x
1.3.2.1.1. Generating Signal Activity Data for Power Analysis 1.3.2.1.2. Generating Standard Delay Output for Power Analysis 1.3.2.1.3. Simulation Glitch Filtering
1.3.2.2. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation x
1.3.2.2.1. RTL Simulation Limitation
1.3.4. Specifying Toggle Rates for Specific Nodes x
1.3.4.1. Clock Node Toggle Rates
1.5. Power Analysis in Modular Design Flows x
1.5.1. Complete Design Simulation Power Analysis Flow 1.5.2. Modular Design Simulation Power Analysis Flow 1.5.3. Multiple Simulation Power Analysis Flow 1.5.4. Overlapping Simulation Power Analysis Flow 1.5.5. Partial Design Simulation Power Analysis Flow 1.5.6. Vectorless Estimation Power Analysis Flow
1.5.5. Partial Design Simulation Power Analysis Flow x
1.5.5.1. Specifying Start and End Time for Signal Activity Calculations
1.6. Scripting Support x
1.6.1. Running the Power Analyzer from the Command–Line
2. Power Optimization x
2.1. Factors Affecting Power Consumption 2.2. Design Space Explorer II for Power-Driven Optimization 2.3. Power-Driven Compilation 2.4. Design Guidelines 2.5. Power Optimization Advisor 2.6. Power Optimization Revision History
2.1. Factors Affecting Power Consumption x
2.1.1. Design Activity and Power Analysis 2.1.2. Device Selection 2.1.3. Environmental Conditions 2.1.4. Device Resource Usage 2.1.5. Signal Activity
2.1.4. Device Resource Usage x
2.1.4.1. Number, Type, and Loading of I/O Pins 2.1.4.2. Number and Type of Hard Logic Blocks 2.1.4.3. Number and Type of Global Signals
2.1.5. Signal Activity x
2.1.5.1. Toggle Rate 2.1.5.2. Static Probability
2.3. Power-Driven Compilation x
2.3.1. Power-Driven Synthesis 2.3.2. Power-Driven Fitter 2.3.3. Area-Driven Synthesis 2.3.4. Gate-Level Register Retiming 2.3.5. Quartus® Prime Compiler Settings 2.3.6. Assignment Editor Options
2.3.1. Power-Driven Synthesis x
2.3.1.1. Memory Block Optimization 2.3.1.2. Power-Aware Logic Mapping 2.3.1.3. Power-Aware Memory Balancing
2.4. Design Guidelines x
2.4.1. Clock Power Management 2.4.2. Pipelining and Retiming 2.4.3. Architectural Optimization 2.4.4. I/O Power Guidelines 2.4.5. Dynamically Controlled On-Chip Terminations (OCT) 2.4.6. Memory Optimization (M20K/MLAB) 2.4.7. DDR Memory Controller Settings 2.4.8. DSP Implementation 2.4.9. Reducing High-Speed Tile (HST) Usage 2.4.10. Unused Transceiver Channels 2.4.11. Periphery Power reduction XCVR Settings
2.4.1. Clock Power Management x
2.4.1.1. Clock Gating 2.4.1.2. Clock Enable in Memory Blocks 2.4.1.3. LAB Clock Power 2.4.1.4. Clock Enables 2.4.1.5. Global Signals 2.4.1.6. Merge Clocks
2.4.1.1. Clock Gating x
2.4.1.1.1. Root Clock Gate 2.4.1.1.2. Sector Clock Gate 2.4.1.1.3. I/O PLL Clock Gate
2.4.1.3. LAB Clock Power x
2.4.1.3.1. LAB-Wide Clock Enable Example
2.4.1.5. Global Signals x
2.4.1.5.1. Viewing Clock Details in the Chip Planner
2.4.6. Memory Optimization (M20K/MLAB) x
2.4.6.1. Implementation 2.4.6.2. Rd/Wr Enables
2.4.11. Periphery Power reduction XCVR Settings x
2.4.11.1. Transceiver Settings 2.4.11.2. I/O Current Strength
2.5. Power Optimization Advisor x
2.5.1. Set Realistic Timing Constraints 2.5.2. Appropriate Device Family 2.5.3. Dynamic Power 2.5.4. Static Power 2.5.5. Appropriate I/O Standards 2.5.6. Use RAM Blocks 2.5.7. Shut Down RAM Blocks 2.5.8. Clock Enables on Logic 2.5.9. Pipeline Logic to Reduce Glitching
2.5.1. Set Realistic Timing Constraints x
2.5.1.1. Find Timing Information
Answers to Top FAQs
1. Power Analysis
2. Power Optimization
3. Power Analysis and Optimization Document Archive
A. Quartus® Prime Pro Edition User Guides

1.3.1. Settings for Power Analysis

You can specify device power characteristics, operating voltage conditions, operating temperature conditions, Power Analyzer settings and thermal settings, in the Operating Settings and Conditions, Power Analyzer Settings, and Thermal pages of the Settings dialog box.
Table 2.  Operating Settings and Conditions
Option Settings
Device power characteristics
  • Maximum—specifies maximum power consumed by the worst-case device. This is the default value for Stratix® 10 and Agilex™ devices.
  • Typical—specifies average power consumed by typical silicon at nominal operating conditions.
Voltage tab Specifies the operating voltage conditions for each power rail in the device, and the supply voltages for power rails with selectable supply voltages.
Temperature tab Specifies the minimum and maximum junction temperature range.
Figure 3.  Operating Settings and Conditions
Figure 4. Power Analyzer Settings
Table 3.  Power Analyzer Settings
Option Settings
Power Analyzer Settings Specifies the Power Analyzer options, including:
  • Run Power Analyzer during compilation—Check this box to turn on power analysis during compilation.
  • Use input file(s) to initialize toggle rates and static probabilities during power analysis—Check this box to use Signal Activity Files or VCD files to initialize toggle rates and static probabilities for power estimation.
  • Write out signal activities used during power analysis—Check this box to write the toggle rates and static probabilities used during power estimation to a file.
  • Power and thermal calculator export file name—specifies the export file name (.qptc) of the design summary that you can import into the Intel® FPGA Power and Thermal Calculator. You can customize this name.
  • Write signal activities to report file—Check this box to have the Power Analyzer write a report file containing the signal activities used during power analysis.
  • Write power dissipation by block to report file—Check this box to have the Power Analyzer report the thermal power dissipation calculated during power analysis, in the Thermal Power Dissipation by Block report panel.
  • Default toggle rate used for input I/O signals—Specify a default toggle rate for use on input I/O pins during power estimation. Can be expressed as a percentage or in transitions/second.
  • Default toggle rate used for remaining signals
    • Use default value—Specify a default toggle rate for use during power estimation on all nodes except I/O pins. This value is used only if no toggle rate is specified through a Signal Activity File, VCD file, or user assignment. Can be expressed as a percentage or in transitions/second.
    • Use vectorless estimation—Turn on this control to use vectorless estimation to fill in undefined toggle rates and static probabilities. If this option is not available, the device family does not support vectorless estimation.
Figure 5. Thermal Settings
Table 4.  Thermal Settings
Option Settings
Thermal Settings Specifies the thermal power analysis temperature conditions, including:
  • Thermal Solver Mode—Select the thermal solver mode to use during power estimation.
  • Junction temperature—Specifies the junction temperature, in °C, used during power estimation.
  • Ambient temperature—Specifies the ambient temperature, in °C, used during power estimation.
  • Cooling solution—Specifies the cooling solution case-to-ambient thermal resistance, in °C per watt.
  • Maximum junction temperature limit—Specifies the maximum junction temperature limit that no part of any die in the package should exceed.
  • Apply additional margin—Specifies, as a percentage, the amount of additional margin to apply to detailed thermal analysis results. Valid values are 0–25%. The default value is 0%. The recommended margin for Agilex™ FPGA portfolio devices is 10%, and for Stratix® 10 devices, 25%.
    Note: For a design compiled in an earlier version of the Quartus® Prime software with the Apply Recommended Margin parameter set to Yes, the current version of Power Analyzer interprets this as an Apply Additional Margin setting of 25%.
  • Temperature measurement method—Select the method to use for reporting temperature sensors for thermal analysis.
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