AN 823: Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel Stratix 10 Devices

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ID 683172
Date 12/18/2017
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Document Table of Contents
Document Table of Contents x
1. Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices
1. Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 823: Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization (ILA)
1. Intel FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Intel® Stratix® 10 Devices

1.5. Test Results

The following table contains the possible results and their definition.

Table 7.  Results Definition
Result Definition
PASS The Device Under Test (DUT) was observed to exhibit conformant behavior.
PASS with comments The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included, such as due to time limitations only a portion of the testing was performed.
FAIL The DUT was observed to exhibit non-conformant behavior.
Warning The DUT was observed to exhibit behavior that is not recommended.
Refer to comments From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.

The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, TL.2, SCR.1, and SCR.2 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 8.  Results for Test Cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, TL.2, SCR.1, and SCR.2
Test L M F SCR K Data rate (Gbps) ADC Sampling Clock (MHz) Link Clock (MHz) Result
1 1 1 8 0 32 6.25 2500 156.25 PASS
2 1 1 8 1 32 6.25 2500 156.25 PASS
3 1 1 8 0 16 6.25 2500 156.25 PASS
4 1 1 8 1 16 6.25 2500 156.25 PASS
5 2 1 4 0 32 6.25 2500 156.25 PASS
6 2 1 4 1 32 6.25 2500 156.25 PASS
7 2 1 4 0 16 6.25 2500 156.25 PASS
8 2 1 4 1 16 6.25 2500 156.25 PASS
9 4 1 2 0 32 6.25 2500 156.25 PASS
10 4 1 2 1 32 6.25 2500 156.25 PASS
11 4 1 2 0 16 6.25 2500 156.25 PASS
12 4 1 2 1 16 6.25 2500 156.25 PASS
13 6 1 1 0 32 6.25 2500 156.25 PASS with comments
14 6 1 1 1 32 6.25 2500 156.25 PASS with comments
15 6 1 1 0 20 6.25 2500 156.25 PASS with comments
16 6 1 1 1 20 6.25 2500 156.25 PASS with comments
17 8 1 1 0 32 6.25 2500 156.25 PASS
18 8 1 1 1 32 6.25 2500 156.25 PASS
19 8 1 1 0 20 6.25 2500 156.25 PASS
20 8 1 1 1 20 6.25 2500 156.25 PASS

The following table shows the results for test cases DL.1, DL.2, DL.3, and DL.4 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 9.  Results for Deterministic Latency Test
Test L M F Subclass K Data rate (Gbps) Sampling Clock(MHz) Link Clock (MHz) Result

Latency

(Link Clock Cycles)
DL.1 1 1 8 1 16/32 6.25 2500 156.25 PASS

195 (K=16)

323 (K=32)
DL.2 1 1 8 1 16/32 6.25 2500 156.25 PASS
DL.3 1 1 8 1 16/32 6.25 2500 156.25 PASS
DL.4 1 1 8 1 16/32 6.25 2500 156.25 PASS
DL.1 2 1 4 1 16/32 6.25 2500 156.25 PASS

115 (K=16)

195 (K=32)
DL.2 2 1 4 1 16/32 6.25 2500 156.25 PASS
DL.3 2 1 4 1 16/32 6.25 2500 156.25 PASS
DL.4 2 1 4 1 16/32 6.25 2500 156.25 PASS
DL.1 4 1 2 1 16/32 6.25 2500 156.25 PASS

67 (K=16)

115 (K=32)
DL.2 4 1 2 1 16/32 6.25 2500 156.25 PASS
DL.3 4 1 2 1 16/32 6.25 2500 156.25 PASS
DL.4 4 1 2 1 16/32 6.25 2500 156.25 PASS
DL.1 6 1 1 1 20/32 6.25 2500 156.25 PASS

53 (K=20)

71 (K=32)
DL.2 6 1 1 1 20/32 6.25 2500 156.25 PASS
DL.3 6 1 1 1 20/32 6.25 2500 156.25 PASS
DL.4 6 1 1 1 20/32 6.25 2500 156.25 PASS
DL.1 8 1 1 1 20/32 6.25 2500 156.25 PASS

53 (K=20)

75 (K=32)
DL.2 8 1 1 1 20/32 6.25 2500 156.25 PASS
DL.3 8 1 1 1 20/32 6.25 2500 156.25 PASS
DL.4 8 1 1 1 20/32 6.25 2500 156.25 PASS

The following figure shows the Signal Tap waveform of the link latency count from the deassertion of SYNC~ to the assertion of the jesd204_rx_link_valid signal. The link latency count (in link clock cycles) measures the first user data output latency.

Figure 6. Deterministic Latency Measurement Ramp Test Pattern Diagram
Level Two Title